Abstract is missing.
- Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAMHui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu. 1-3 [doi]
- A three-stage LDO with active feedback frequency compensation and slew-rate enhancementTongning Hu, Bo Wang, Ke Lin, Yi Peng, Xin'an Wang. 1-4 [doi]
- Low-complexity synchronizer used in DC-OFDM UWB systemBing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren. 1-4 [doi]
- A CMOS low-noise amplifier for BCC applicationsZhige Zou, Wuyue Wang, Jianming Lei, Guoyi Yu, Xuecheng Zou. 1-4 [doi]
- A linearized VBE bandgap voltage reference with wide temperature rangeXiaofei Chen, Fanhong Liu, Xuecheng Zou, Shuangxi Lin. 1-4 [doi]
- Reduced complexity implementation of quasi-cyclic LDPC decoders by parity-check matrix reorderingJianing Su, Zhenghao Lu. 1-4 [doi]
- A 2Mb ReRAM with two bits error correction codes circuit for high reliability applicationJianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin. 1-4 [doi]
- A process variation insensitive bandgap reference with self-calibration techniqueLing Du, Ning Ning, Kejun Wu, Yang Liu, Qi Yu. 1-4 [doi]
- A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPANNagarajan Mahalingam, Yisheng Wang, Kaixue Ma, Shouxian Mou, Kiat Seng Yeo. 1-4 [doi]
- Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifierYang Zhao, Bill Yang Liu, Zhiliang Hong. 1-4 [doi]
- VCCS controlled LDO with small on-chip capacitorQiuli Li, Yao Qian, Danzhu Lu, Zhiliang Hong. 1-4 [doi]
- Controlling-value-based power gating considering controllability propagation and power-off probabilityZhe Du, Yu Jin, Shinji Kimura. 1-4 [doi]
- Power and resource aware scheduling with multiple voltagesHaoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura. 1-4 [doi]
- Highly stable data SRAM-PUF in 65nm CMOS processXuelong Zhang, Pengjun Wang, Yuejun Zhang. 1-4 [doi]
- A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoderCong Liu, Weiwei Shen, Tianlong Ma, Yibo Fan, Xiaoyang Zeng. 1-4 [doi]
- A collision and tag number detector for UHF RFID reader conforming to EPC Gen2 protocolLingzhi Fu, Xiao Yan, Junyu Wang. 1-4 [doi]
- Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit designZuochang Ye. 1-4 [doi]
- A GFSK transceiver for IEEE Std. 802.15.4g used in ChinaMaoqiang Duan, Xiaoli Huang, Zhijia Yang. 1-4 [doi]
- Characteristics of n-MOSFETs with stress effects from neighborhood devicesWei Tai, Lele Jiang, Wang Lei, Song Wen, Lifu Chang, Yuhua Cheng. 1-3 [doi]
- A new channel emulator for low voltage broadband power line communicationYan Zhao, Xiaofang Zhou, Chao Lu. 1-4 [doi]
- Design philosophy of hysteretic controller for DC-DC switching convertersJian Lv, Simon S. Ang. 1-4 [doi]
- Piezoelectric force microscopy study of local bipolar diode current dependence of preferential domain orientation in BiFeO3 thin films with different thicknessesLong He, Zhihui Chen, Anquan Jiang. 1-4 [doi]
- Self-synchronous circuit designs, SSFPGA and SSRSA for low voltage autonomous control and tamper resistivityMakoto Ikeda. 1-4 [doi]
- Theory and hardware implementation of an analog-to-Information Converter based on Compressive SensingSujuan Liu, Meihui Zhang, Wenshu Jiang, Junshan Wang, Peipei Qi. 1-4 [doi]
- A 20 Gb/s Limiting Amplifier in 65nm CMOS technologyRui He, Jianfei Xu, Na Yan, Min Hao. 1-4 [doi]
- A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networksJie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng. 1-4 [doi]
- Improved unified interconnect unit for high speed and scalable FPGALei Li, Jian Wang, Jinmei Lai. 1-4 [doi]
- Incremental symbolic construction for topological modeling of analog circuitsHanbin Hu, Guoyong Shi, Yan Zhu. 1-4 [doi]
- Mixed-signal SoC design and low power research for tire pressure monitoring systemsYangyang Guo, Liji Wu, Tengfei Zhai, Xiao Yu, Xiangmin Zhang. 1-4 [doi]
- Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuitsGuangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang. 1-4 [doi]
- A fast and accurate automatic frequency calibration scheme for frequency synthesizerYan Dun, Jiancheng Li, Songting Li, Xiaochen Gu, Chong Huang. 1-4 [doi]
- A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM systemJiasen Huang, Hao Chen, Junyan Ren, Fan Ye. 1-4 [doi]
- Current-mode square-wave converter with current-rectifying function employing MOCCIISen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang. 1-4 [doi]
- A 300MHz 10b time-interleaved pipelined-SAR ADCLu Sun, Yuxiao Lu, Tingting Mo. 1-4 [doi]
- Fast transistor-level circuit simulation and variational analysis via the ultra-compact virtual source modelYang Zhang, Quan Chen, Ngai Wong. 1-4 [doi]
- FFTPL: An analytic placement algorithm using fast fourier transform for density equalizationJingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng. 1-4 [doi]
- A practical method for auto-design and optimization of DC-DC buck converterGuanming Huang, Dian Zhou, Xuan Zeng, Shengguo Wang. 1-4 [doi]
- A novel equalizer for the high-loss backplane at Nyquist frequencyYou Li, Feng Zhang, Yumei Zhou. 1-4 [doi]
- Automatic gain control algorithm with high-speed and double closed-loop in UWB systemBing Jing, Yuankun Xue, Fan Ye, Ning Li, Junyan Ren. 1-4 [doi]
- A CMOS PGA with DCOC and I/Q mismatch calibrationXingpeng Pan, Rui Guan, Dongpo Chen. 1-4 [doi]
- Evaluation of Cyanoethyl Pullulan material as the dielectric layer for EWOD devicesJianfeng Chen, Yuhua Yu, Xiangyu Zeng, Jian Li, Jia Zhou. 1-4 [doi]
- AHardware implementation of DES with combined countermeasure against DPAXiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui. 1-4 [doi]
- A DLL based low-phase-noise clock multiplier with offset-tolerant PFDYuwen Wang, Fan Ye, Junyan Ren. 1-4 [doi]
- A new splitting graph construction algorithm for SIAR routerJinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou. 1-4 [doi]
- Analytic models for electric potential and subthreshold swing of the dual-material double-gate MOSFETPing Xiang, Zhihao Ding, Guangxi Hu, Hui Chol Ri, Ran Liu 0001, Lingli Wang, Xing Zhou. 1-4 [doi]
- Parameter and UVM, making a layered testbench powerfulGeng Zhong, Jian Zhou, Bei Xia. 1-4 [doi]
- Simulation design for continuous separating and 3D focusing of particles based on inertial microfluidicsJian Li, Xiangyu Zeng, Jia Zhou. 1-4 [doi]
- Device parameter variations of n-MOSFETS with dog-bone layouts in 65nm and 40nm technologiesLele Jiang, Song Wen, Wei Tai, Wang Lei, Lifu Chang, Yuhua Cheng. 1-3 [doi]
- A two-phase floorplanning approach for Application-specific Network-on-ChipShuang Yu, Fen Ge, Gui Feng, Ning Wu. 1-4 [doi]
- The decimator with multiplier-free realizations for high precision ADC applicationsYiwu Yao, Kailiang Zhang, Hongming Chen, Yuhua Cheng. 1-4 [doi]
- Design and analysis of nano-scale bulk FinFETsJong-Ho Lee, Kyu-Bong Choi, Jongmin Shin. 1-3 [doi]
- Barrier and low k polish with a novel alkaline barrier slurry combining with FA/O chelating agentJing-Bo Xu, Feng Hui, Wen-Zhong Xu, Xu Wang, Peng-Fei Nan, Yu-ling Liu, Xin-Ping Qu. 1-4 [doi]
- Low noise design and measurement of 32-channel X-ray ROICDan Liu, Chuan Jin. 1-4 [doi]
- A high throughput FPGA embedded DSP architecture designHanyang Xu, Jinmei Lai. 1-4 [doi]
- An NFC system with high sensitivity based on SDRLongxiang Zhang, Hantian Xu, Yingbo Dai, Hao Min. 1-4 [doi]
- A high-resolution TDC implemented in a 90nm process FPGAJinmei Lai, Yanquan Luo, Qi Shao, Lichun Bao, Xueling Liu. 1-3 [doi]
- A test pattern selection method for dynamic burn-in of logic circuits based on ATPG techniqueXuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee. 1-4 [doi]
- A fast 8×8 IDCT algorithm for HEVCTianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng. 1-4 [doi]
- Incremental 3D NoC synthesis based on physical-aware router merging algorithmYuanyuan Li, Ning Xu, Yuchun Ma, Jinian Bian. 1-4 [doi]
- Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag designZhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, Sheng-Guo Wang. 1-4 [doi]
- Secure systolic architecture for montgomery modular multiplication algorithmQi Yang, Xiaoting Hu, Zhongping Qin. 1-4 [doi]
- Design of 13.56MHz power recovery circuit with signal transmission for contactless bank IC cardYang Li, Liji Wu, Xiangmin Zhang. 1-4 [doi]
- VLSI design of fuzzy-decision bit-flipping QC-LDPC decoderWenzhe Zhao, Minjie Lv, Hongbin Sun, Nanning Zheng, Tong Zhang 0002. 1-4 [doi]
- 3D hybrid modeling of substrate coupling noise in lightly doped mixed-signal ICsYongsheng Wang, Fang Li, Hualing Yang, Yonglai Zhang, Yanhui Ren. 1-4 [doi]
- Ag dendrite formed on the Cu pyramids as SERS substratePeng-Fei Nan, Xu Wang, Xin-Ping Qu. 1-3 [doi]
- A FPGA real-time stereo vision system with luminance control and projected patternYuan Xu, Haodong Yao, Liwei Gong, Mingcheng Zhu, Robert K. F. Teng. 1-4 [doi]
- MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip supportDexue Zhang, Xiaoyang Zeng, Zongyan Wang, Weike Wang, Xinhua Chen. 1-4 [doi]
- Variation-aware subthreshold logic circuit designHiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. 1-4 [doi]
- Design of frequency synthesizer in frequency-hopping transceiverYong Xu, Fei Zhao, Chen Hu, Zheng Sun, Yuanliang Wu, Jianwen Lu. 1-4 [doi]
- Design of dual-wideband low noise amplifier base on common gate topologyMeng-Ting Hsu, Po-Yu Lee, Yu-Zhang Huang. 1-4 [doi]
- A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase GraphJianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang. 1-5 [doi]
- Oscillator phase noise verification accounting for process variationsLiuxi Qian, Dian Zhou, Xuan Zeng, Shengguo Wang. 1-4 [doi]
- A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applicationsZhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung-Len Lee. 1-4 [doi]
- A novel inverse quantization algorithm based on Taylor series for digital audio codecsFan Liu, Junfeng Zhu, Xiaozong Huang, Xun Xiang. 1-3 [doi]
- A high performance VLSI architecture for integer motion estimation in HEVCYuan Xu, Jinsong Liu, Liwei Gong, Zhi Zhang, Robert K. F. Teng. 1-4 [doi]
- A reconfigurable floating-point FFT architectureChenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan. 1-4 [doi]
- Integrated silicon RF front-end solutions for mobile communicationsAlvin Joseph, Randy Wolf. 1-4 [doi]
- Implementation of H.264 intra-frame encoding on clustered stream architecturesZhixiang Chen, Yi Fang, Fang Wang, Zhaolin Li. 1-4 [doi]
- Full Software Radio transceiversYann Deval, Francois Rivet, Yoan Veyrac, Nicolas Regimbal, Patrick Garrec, Richard Montigny, Didier Belot, Thierry Taris. 1-4 [doi]
- A nonlinear weighted PID controlled 12V to 1V DC-DC converter with transient suppressionChu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang, Wei-Chih Wang. 1-4 [doi]
- Design of novel high speed dual-modulus prescaler based on new optimized structureZheng Sun, Yong Xu, Chen Hu, Guangyan Ma, Yuanliang Wu, Ying Huang. 1-4 [doi]
- Three-dimensional on-chip inductor design based on through-silicon viasFeng Liang, Si-Qi Zhao, Aobo Chen, Gaofeng Wang. 1-3 [doi]
- A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DACJixuan Xiang, Jian Mei, Hao Chang, Fan Ye. 1-4 [doi]
- Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designsJixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian. 1-4 [doi]
- A novel architecture scheme with adaptive pipeline coupling technique for DSP processor designZheng Tang, Jing Xie, Zhigang Mao. 1-4 [doi]
- A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoCNingyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu. 1-4 [doi]
- A small-area low-power ADC array for image sensor applicationsShengyou Zhong, Libin Yao, Jiqing Zhang. 1-4 [doi]
- A high-performance current sensing circuit with full-phase sampling capabilityZe-kun Zhou, Haiwu Xie, Yue Shi, Chuankui Wu, Jiangang Huang, Xin-ming, Bo Zhang. 1-4 [doi]
- Timing and resource constrained leakage power aware scheduling in high-level synthesisNan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura. 1-4 [doi]
- A turbo decoder implementation for LTE downlink mapped on a multi-core processor platformQing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng. 1-4 [doi]
- A novel Operational Transconductance Amplifier with high Gm using improved differential current redistribution technique (DCRT)Jing Zhu, Yunwu Zhang, Weifeng Sun, Shengli Lu. 1-4 [doi]
- Background calibration techniques for multistage pipelined ADCs with dynamic element matching and pseudorandom noiseLongcheng Que, Yiying Du, Jian Lv, Yadong Jiang. 1-4 [doi]
- Soft error immunity of subthreshold SRAMMasanori Hashimoto. 1-4 [doi]
- TSVs-aware floorplanning for 3D integrated circuitJieliang Lu, Qin Wang, Jing Xie, Zhigang Mao. 1-4 [doi]
- Statistical simulation methods for circuit performance analysisTakashi Sato. 1-4 [doi]
- Ultra-low noise and high PSR LDO designJiangpeng Wang, Jinguang Jiang. 1-4 [doi]
- FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architectureWenqing Lu, Gerald E. Sobelman, Xiaofang Zhou, Junyan Ren. 1-4 [doi]
- Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processorHaopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao. 1-4 [doi]
- PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxideChun-Min Zhang, Qing-Qing Sun, Peng-fei Wang, David Wei Zhang. 1-4 [doi]
- A new high performance RF LDMOS with vertical n+n-p-p+ drain structureXiaofei Chen, Yading Shen, Xuecheng Zou, Shuang-Xi Lin, Wanghui Zou. 1-4 [doi]
- Low overhead task migration mechanism in NoC-based MPSoCFangfa Fu, Liang Wang, Yu Lu, Jinxiang Wang. 1-4 [doi]
- A high-throughput LDPC decoder for optical communicationDi Wu, Yun Chen, Yuebin Huang, Yeong-Luh Ueng, Lirong Zheng, Xiaoyang Zeng. 1-4 [doi]
- Folding and interpolation ADC design methodologySiqiang Fan, Albert Z. Wang, Bin Zhao. 1-4 [doi]
- Design of a high throughput configurable variable-length FFT processor based on switch network architectureRenfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng. 1-4 [doi]
- An improved analytical series resistance model for on-chip stacked inductorsWanghui Zou, Xiaofei Chen, Xuecheng Zou. 1-4 [doi]
- A single branch charge pump without overstress for RFID tagLei Cai, Xiaocheng Gu, Jiancheng Li, Chong Huang, Cong Li, Qin Qin, Junping Guo. 1-4 [doi]
- Compact and portable chemiluminescence detector for glucoseKaidi Zhang, Guowei Tao, Xiangyu Zeng, Wenjie Sheng, Jia Zhou. 1-4 [doi]
- An integrated development environment for reconfigurable operators arrayShanshan Yong, Xin'an Wang, Ying Cao, Yawei Lu, Zheng Xie. 1-4 [doi]
- A configurable distributed systolic array for QR decomposition in MIMO-OFDM systemsYong-xu Zhu, Bin Wu, Yumei Zhou, Kaifeng Xia, Lu Sun. 1-5 [doi]
- A power-constrained contrast enhancement algorithm for AMOLED display using histogram segmentationWenhua Qiang, Qi Zhang, Wei Miao, Guohong Li, Hui Wang, Songlin Feng. 1-4 [doi]
- Low-resistance wide-voltage-range analog switch for implantable neural stimulatorsYunpu Hu, Songping Mai, Yixin Zhao, Chun Zhang. 1-4 [doi]
- A new fast median filtering algorithm based on FPGALeiou Wang. 1-4 [doi]
- Design automation of analog circuit considering the process variationsDian Zhou, Guanming Huang. 1-4 [doi]
- A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulatorZemin Feng, Chixiao Chen, Fan Ye, Jun Xu 0011, Junyan Ren. 1-4 [doi]
- Interconnection allocation between functional units and registers in High-Level SynthesisCong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu. 1-4 [doi]
- Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensingNingxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin. 1-4 [doi]
- New DfT architectures for 3D-SICs with a wireless test portYibo He, Xiaole Cui, Chung-Len Lee, Xiaoxin Cui, Yufeng Jin. 1-4 [doi]
- A 2.4 mW, 11.7±0.4dB, 3 to 5 GHz wide-band LNA for super-regenerative IR-UWB receiverYi Peng, Bo Wang, Tongning Hu, Jinhai Zhang, Xin'an Wang. 1-4 [doi]
- The annealing effect of chemical vapor deposited grapheneY.-L. Shen, P. Zhou, L.-H. Wang, Q. Q. Sun, Q. Q. Tao, P. F. Wang, S. J. Ding, D. W. Zhang. 1-4 [doi]
- FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-AmpMinghua Li, Dian Zhou, Sheng-Guo Wang, Xuan Zeng. 1-4 [doi]
- A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design techniqueZitao Shi, Xin Wang, Albert Z. Wang, Yuhua Cheng. 1-4 [doi]
- Developing a design system to help reduce design cycle timeJing Li, Xingang Wang. 1-4 [doi]
- Efficient implementation of 3780-point FFT on a 16-core processorHaoFan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng. 1-4 [doi]
- A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensorBiao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng. 1-4 [doi]
- A novel digital controller for boost PFC converter with high power factor and fast dynamic responseDaying Sun, Weifeng Sun, Qing Wang, Shen Xu, Shengli Lu. 1-4 [doi]
- Interconnect waveform calculation method with parameter variationGoro Suzuki, Ryo Yamanaka. 1-4 [doi]
- Design and test of an SRAM chipWenbin Liu, Jinhui Wang, Ligang Hou, Hongyan Yang, Jianbo Kang. 1-4 [doi]
- Calibration for split capacitor DAC in SAR ADCZhe Li, Yuxiao Lu, Tingting Mo. 1-4 [doi]
- RWCap2: Advanced floating random walk solver for the capacitance extraction of VLSI interconnectsWenjian Yu. 1-4 [doi]
- Co-design of ESD protection and LNA in RFICYueguo Hao, Qiao Zhang, Xiaopeng Bai, Zitao Shi, Huainan Ma, Yuhua Cheng. 1-4 [doi]
- A novel test scheme for NAND flash memory based on built-in oscillator ringSi Chen, Xiaole Cui, Chung-Len Lee. 1-4 [doi]
- Design of a novel all-CMOS low power voltage reference circuitYusen Xu, Wei Hu, Fengying Huang, Jiwei Huang. 1-4 [doi]
- An interference miss isolation mechanism based on skewed mapping for shared cache in Chip MultiprocessorsAnwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang. 1-4 [doi]
- Building-in reliability in BCD (Bipolar-CMOS-DMOS) technologiesJifa Hao, T. E. Kopley. 1-4 [doi]
- Low jitter clock driver for high-performance pipeline ADCYun Chen, Chaojie Fan, Jianjun Zhou. 1-4 [doi]
- Scan-based attack against Trivium stream cipher independent of scan structureMika Fujishiro, Masao Yanagisawa, Nozomu Togawa. 1-4 [doi]
- Two sides of pulse quenching effect on the single-event transient pulse width at circuit-levelBin Liang, Yankang Du. 1-4 [doi]
- Ultra-low frequency P(VDF-TrFE) piezoelectric energy harvester on flexible substrateZhaoyang Pi, Lun Zhu, Jingwei Zhang, Dongping Wu, David Wei Zhang, Zhi-Bin Zhang, Shi-Li Zhang. 1-4 [doi]
- Distributed task migration for thermal hot spot reduction in many-core microprocessorsZao Liu, Xin Huang, Sheldon X.-D. Tan, Hai Wang, He Tang. 1-4 [doi]
- Dual control mode AGC for wireless communication systemFan Meng, Rui Guan, Dongpo Chen. 1-4 [doi]
- A 2D mesh NoC with self-configurable and shared-FIFOs routersWei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng. 1-4 [doi]
- Power grid simulation using matrix exponential method with rational Krylov subspacesHao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng. 1-4 [doi]
- A 800nW high-accuracy RC oscillator with resistor calibration for RFIDJinhai Zhang, Bo Wang, Yi Peng, Tongning Hu, Xin'an Wang. 1-4 [doi]
- An adaptive Q factor tuning and input impedance matching method for ultra-low power front end of UHF RFID tagChong Huang, Xiaochen Gu, Lei Cai, Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li. 1-4 [doi]
- Design of drain-gate transformer feedback VCO with body-biasingMeng-Ting Hsu, Jie-An Huang, Yao-Yan Lee. 1-4 [doi]
- A CMOS passive mixer-first receiver front-end for UHF RFID ReaderZhiheng Lin, Xi Tan, Hao Min. 1-4 [doi]
- Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithmFei Sun, Pengjun Wang, Haizhen Yu. 1-4 [doi]
- An integrated stacked transformer with large inductance at 900MHzHantian Xu, Longxiang Zhang, Xi Tan, Hao Min. 1-4 [doi]
- A power-efficient network-on-chip for multi-core stream processorsGuoyue Jiang, Fang Wang, Zhaolin Li, Shaojun Wei. 1-4 [doi]
- A 10-bit pipelined ADC with improved S/H circuit for CMOS image sensorYiling Ding, Qi Zhang, Ning Wang, Dunshan Yuan, Guohong Li, Hui Wang, Songlin Feng. 1-4 [doi]
- A low spur CMOS phase-locked loop with wide tuning range for CMOS Image SensorZhiqing Chen, Qi Zhang, Ning Wang, Dunshan Yuan, Guohong Li, Hui Wang, Songlin Feng. 1-4 [doi]
- A novel dynamic element match technique in current-steering DACBaoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang. 1-4 [doi]
- A high conversion coefficient RF front end of ultra-low power RFID tagChong Huang, Xiaochen Gu, Lei Cai, Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li. 1-4 [doi]
- A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receiversZhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue. 1-4 [doi]
- Enhanced error correction against multiple-bit-upset based on BCH code for SRAMWeijia Ma, Xiaole Cui, Chung-Len Lee. 1-4 [doi]
- Integrated amorphous-Si TFT circuits for gate drivers on LCD panelsNan-Xiong Huang, Hsi Rong Han, Wen Tui Liao, Chih-Hung Huang, Wen Chun Wang, Miin-Shyue Shiau, Ching-Hwa Cheng, Hong-Chong Wu, Heng-Shou Hsu, Juin J. Liou, Shry-Sann Liao, Ruei-Cheng Sun, Guang-Bao Lu, Don-Gey Liu. 1-4 [doi]
- Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processorsShota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi. 1-4 [doi]
- Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processorsHuatao Zhao, Jiongyao Ye, Yuxin Sun, Takahiro Watanabe. 1-4 [doi]
- Transition metal dichalcogenides - A new material class for semiconductor electronics?Frank Schwierz. 1-4 [doi]
- Polarity dependent of gate oxide breakdown from measurementsShili Wu, Xiaowei He, Yuwei Liu, Guoan Chen. 1-2 [doi]
- An 8-bit 100KS/s low power successive approximation register ADC for biomedical applicationsXiao Yan, Lingzhi Fu, Junyu Wang. 1-4 [doi]
- Frame synchronization for a narrow-band power line OFDM communication systemXiaoxue Yu, Hong Liu, Hao Min. 1-4 [doi]
- H.264 video parallel decoder on a 24-core processorShikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng. 1-4 [doi]
- Design and implementation of transaction level processor based on UVMYingke Gao, Diancheng Wu, Quanquan Li, Tiejun Zhang, Chaohuan Hou. 1-4 [doi]
- Key component designs of subthreshold baseband processors in passive RF deviceWeiwei Shi, Oliver Chiu-sing Choy, Robert K. F. Teng. 1-4 [doi]
- +Si-HfO2-Ni RRAMD. Y. Lu, X. A. Tran, H. Y. Yu, D. M. Huang, Y. Y. Lin, S. J. Ding, P. F. Wang, Ming Fu Li. 1-4 [doi]
- An equalization system for 2 series-connected Li-ion batteriesJinguang Jiang, Sen Li. 1-3 [doi]
- A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the flyShengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao. 1-4 [doi]
- Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCsWei Zhong, Song Chen, Yang Geng, Takeshi Yoshimura. 1-4 [doi]
- A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm opticalQuan Pan, Zhengxiong Hou, Yipeng Wang, C. Patrick Yue. 1-4 [doi]
- A CMOS synchronous time amplifierSiliang Hua, Donghui Wang, Yan Liu. 1-4 [doi]
- Sparse basis pursuit on automatic nonlinear circuit modelingYu-Chung Hsiao, Luca Daniel. 1-4 [doi]
- Low-power high-speed communication with short-millimeter-wave CMOS transceiversMinoru Fujishima. 1-4 [doi]
- A proposed data converter for current signal with temperature-compensated sample resistorXiaozong Huang, Luncai Liu, Liu Fan, Jing Zhang, Wengang Huang, Yanlin Zhang, Lei Yu. 1-3 [doi]
- A reference spur estimation method for integer-N PLLsBo Wang, Jinhai Zhang, Edouard Ngoya. 1-4 [doi]
- Design and implementation of a dynamic loop buffer by reusing the instruction bufferQi Wang, Ying-ke Gao, Dong-hui Wang, Tiejun Zhang, Chaohuan Hou. 1-4 [doi]
- Graphene electronics and photonics (Invited)Tony Low. 1-2 [doi]
- Network functions for characterization of elementary semiconductor nanostructuresThomas Wong, Tao Shen. 1-4 [doi]
- Weight-based FPGA placement algorithm with wire effect consideredHuagang Li, Jian Wang, Jinmei Lai. 1-4 [doi]
- Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) designChao Liang. 1-4 [doi]
- Transform-based fast mode and depth decision algorithm for HEVC intra predictionGang He, Dajiang Zhou, Satoshi Goto. 1-4 [doi]
- Analog routing considering min-area constraintWeijie Chen, Hailong Yao, Yici Cai, Qiang Zhou. 1-4 [doi]
- Implementation of an embedded dual-core processor for portable medical electronics applicationsYingrui Chen, Teng Wang, Xin'an Wang, Ziyi Hu. 1-4 [doi]
- A high-efficiency high-power BUCK converter based on fully N-type power transistorsZhuo Wang, Yuan Dong, Xia Wang, Zekun Zhou, Xin-ming, Bo Zhang. 1-4 [doi]
- RF design and technology supporting Active Safety in automotive applicationsMassimo Gimignani, Mario Paparo, Domenico Rossi, Salvo Scaccianoce. 1-4 [doi]
- Design and implementation of RSA for dual interface bank IC cardJiajia Shao, Liji Wu, Xiangmin Zhang. 1-4 [doi]
- A novel architecture of local memory for programmable SIMD vision chipZhe Chen, Jie Yang, Cong Shi, Nanjian Wu. 1-4 [doi]
- An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technologyLiwei Gong, Yuan Xu, Zhi Zhang, Weiwei Shi, Robert K. F. Teng. 1-4 [doi]
- Lithography hotspot detection and mitigation in nanometer VLSIJhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan. 1-4 [doi]
- Graph Steiner tree construction and its routing applicationsJun Dong, Hengliang Zhu, Min Xie, Xuan Zeng. 1-4 [doi]
- A temperature sensing front-end using CMOS substrate PNP transistorsDexin Kong, Ting Yu, Fengqi Yu. 1-4 [doi]
- An area-efficient implementation of ΣΔ ADC multistage decimation filterChenxi Deng. 1-5 [doi]
- A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADCTing Li, Dongbing Fu, Yong Zhang, Yan Wang, Lu Liu, Xu Wang. 1-4 [doi]
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- Digital calibration techniques for interstage gain nonlinearity in pipelined ADCsChaojie Fan, Wenjie Pan, Ke Wang, Jianjun Zhou. 1-4 [doi]
- A clocked differential switch logic using floating-gate MOS transistorsGuoqiang Hang, Yang Yang, Peiyi Zhao, Xiaohui Hu, Xiaohu You. 1-4 [doi]
- A parallel sparse linear system solver for large-scale circuit simulation based on Schur ComplementLiuxi Qian, Dian Zhou, Xuan Zeng, Fan Yang, Shengguo Wang. 1-4 [doi]
- A semi-auto interactive 2D-to-3D video conversion technique based on edge detectionTianyi Hu. 1-4 [doi]
- A 10Gb/s analog equalizer in 0.18um CMOSLinghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang. 1-4 [doi]
- Fabrication of silicon-based MEMS capacitive microphone structure with thin starting waferXiaoxu Kang, Chao Yuan, Qingyun Zuo, Changwa Yao, Shoumian Chen, Yuhang Zhao, Yilin Yan, Yuanjun Xu, Weiping Zhou. 1-3 [doi]
- Design of an optimized low-latency interrupt controller for IMS-DPUZijia Guo, Teng Wang, Xin'an Wang, Ziyi Hu. 1-4 [doi]
- Implementation of a configurable MIMO detector with complex K-best algorithmJieqiong Cheng, Junsong Zheng, Xiaofang Zhou, Linshan Zhang. 1-4 [doi]
- An empirical model for static I-V characteristics of double gate tunneling field effect transistorD. M. Huang, C. J. Yao, D. H. Shi, M. F. Li. 1-4 [doi]
- A wideband CMOS variable-gain low noise amplifier with novel attenuatorTao Cheng, Tao Yang, Xin Wang, Zhangwen Tang. 1-4 [doi]
- A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessorsXiantuo Rao, Teng Wang, Xin'an Wang, Yinhui Wang. 1-4 [doi]
- Low power instruction cache design based on branch execution tracksQuanquan Li, Qi Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou. 1-4 [doi]
- A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technologyShuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang. 1-4 [doi]
- Design of low power UWB CMOS LNA using RC feedback and body-bias technologyMeng-Ting Hsu, Yu-Chang Hsieh, An-Cheng Ou. 1-4 [doi]
- A novel current-mode versatile filter employing CCCDCC and MO-OTASen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang. 1-5 [doi]
- A fast multi-core virtual platform and its application on software developmentZongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng. 1-4 [doi]
- Positionable wearable fall detection system for elderly assisted living applicationsJie Cheng, Yun Chen, Wenxu Bao, YuanZhou Hu, Na Ding, Xiaoyang Zeng. 1-4 [doi]
- Design of a hybrid reconfigurable coprocessorXiang Wang, Su Zhang, Wei Ni, Yukun Song, Yanhui Yang, Jichun Bu. 1-4 [doi]
- An acceleration method by GPGPU for analytical placement using quasi-Newton methodSyota Kuwabara, Yukihide Kohira, Yasuhiro Takashima. 1-4 [doi]
- Toward microwave integrated circuits on flexible substrates (invited)Jung-Hun Seo, Weidong Zhou, Zhenqiang Ma. 1-4 [doi]
- Robust current-mode on-chip interconnect signaling scheme in deep submicronXinsheng Wang, Mingyang Hu, Mingyan Yu. 1-4 [doi]
- A current mode sense amplifier with self-compensation circuit for SRAM applicationHeqing Xu, Song Jia, Jiyu Chen, Yuan Wang, Gang Du. 1-4 [doi]
- An integrated zigbee transmitter and DC-DC converter on 0.18μm HV RF CMOS technologyChaojiang Li, Dawn Wang, Myra Boenke, Ted Letavic, John Cohn. 1-4 [doi]
- Genetic Algorithm based pipeline scheduling in high-level synthesisXiaohao Gao, Takeshi Yoshimura. 1-4 [doi]
- A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation techniqueYongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren. 1-4 [doi]
- Compact modeling of the diode reverse recovery effect for leading developments of power electronic applicationsMasataka Miyake, Kai Matsuura, Akifumi Ueno. 1-4 [doi]
- The timing control design of 65nm block RAM in FPGAXinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai, Lichun Bao, Xueling Liu. 1-4 [doi]
- Quantitative analysis for high speed interpolated/averaging ADCHe Tang, Yong Peng, Xiang Lu, Hai Wang, Albert Z. Wang. 1-4 [doi]
- A cost-effective method for masking transient errors in NoC flit typeJiajia Jiao, Yuzhuo Fu. 1-4 [doi]
- A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DACJian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren. 1-4 [doi]
- An efficient low-cost fixed-point digital down converter with modified filter bankHanyu Wang, Jinxiang Wang, Yu Lu, Fangfa Fu. 1-4 [doi]
- Analytical model of the coupling capacitance between cylindrical through silicon via and horizontal interconnect in 3D ICWenjian Yu, Siyu Yang, Qingqing Zhang. 1-4 [doi]
- Gate oxide enhancement for whole chip ESD design between different power domainsHongwei Li, Guang Chen, Huijuan Cheng. 1-4 [doi]
- A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETsGao Hong-Wun, Te-Kuang Chiang. 1-3 [doi]
- Low power design for FIR filterGaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng. 1-4 [doi]
- A design of configurable image enhancement unitZhiyuan Xue, Huan Ying, Yingke Gao, Tiejun Zhang, Donghui Wang, Chaohuan Hou. 1-4 [doi]
- Networking industry trends in ESD protection for high speed IOsRichard Wong, Rita Fung, Shi-Jie Wen. 1-4 [doi]
- A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architectureGui Feng, Fen Ge, Shuang Yu, Ning Wu. 1-4 [doi]
- Analysis inductively coupling wireless connection in 3D packageBaocun Wang, Guoyi Yu, Xiaofei Chen, Li Zhang, Xavier Zou. 1-5 [doi]
- An automatic peak-valley current mode step-up/step-down DC-DC converter with smooth transitionYanzhao Ma, Shaoxi Wang, Shengbing Zhang, Xiaoya Fan. 1-4 [doi]
- Highly flexible WBAN transmit-receive system based on USRPTianchan Guan, Jun Han, Xiaoyang Zeng. 1-4 [doi]
- AVCO with F-V linearization techniques for CNS applicationPeng Chen, Rui Guan, Dongpo Chen. 1-4 [doi]
- Investigation on effectiveness of series gate resistor in CDM ESD protection designsYuanzhong (Paul) Zhou, Alan W. Righter, Jean-Jacques Hajjar. 1-4 [doi]
- A universal framework of dual-use model for both performance and functionality based on the abstract state machineZheng Xie, Xin'an Wang, Zhibin Lian, Qiuping Li, Shanshan Yong. 1-4 [doi]
- An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMPWeijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng. 1-4 [doi]
- A low-power ternary content-addressable memory using pulse current based match-line sense amplifiersMeng-chou Chang, Shih-Ju Tsai. 1-4 [doi]
- CMOS 1.2V bandgap voltage reference designChao Feng, Jinhui Wang, Wei Wu, Ligang Hou, Jianbo Kang. 1-4 [doi]
- An optimized hardware architecture for intra prediction in H.264 decoderQi Wang, Quanquan Li, Shi Chen, Tiejun Zhang, Chaohuan Hou. 1-4 [doi]
- A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch driversYuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu 0011, Junyan Ren. 1-4 [doi]
- A sorting-based IO connection assignment for flip-chip designsRan Zhang, Xue Wei, Takahiro Watanabe. 1-4 [doi]