An area-efficient implementation of ΣΔ ADC multistage decimation filter

Chenxi Deng. An area-efficient implementation of ΣΔ ADC multistage decimation filter. In IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013. pages 1-5, IEEE, 2013. [doi]

Abstract

Abstract is missing.