Xuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee. A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. In IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013. pages 1-4, IEEE, 2013. [doi]
Abstract is missing.