Table of Contents

• Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAMYiran Chen, Hai Li, XiaoBin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang. 1-6 [doi]
• Low-power and high-performance technologies for mobile SoC in LTE eraToshihiro Hattori. 1-2 [doi]
• Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGABenjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. 3-8 [doi]
• A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMsHamed F. Dadgour, Muhammad M. Hussain, Kaustav Banerjee. 7-12 [doi]
• Variation-aware clock network design methodology for ultra-low voltage (ULV) circuitsXin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim. 9-14 [doi]
• Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation studySubho Chatterjee, Sayeef Salahuddin, Satish Kumar, Saibal Mukhopadhyay. 13-18 [doi]
• Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensationMing-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang. 15-20 [doi]
• Variation aware performance analysis of gain cell embedded DRAMsWei Zhang, Ki Chul Chun, Chris H. Kim. 19-24 [doi]
• Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOSTadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. 21-26 [doi]
• Low-power dual-element memristor based memory designDimin Niu, Yiran Chen, Yuan Xie. 25-30 [doi]
• FPGA glitch power analysis and reductionWarren Wai-Kit Shum, Jason Helge Anderson. 27-32 [doi]
• Power-efficient variation-aware photonic on-chip network managementMoustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun. 31-36 [doi]
• SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architecturesMichael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich. 33-38 [doi]
• VAIL: variation-aware issue logic and performance binning for processor yield and profit improvementSomnath Paul, Swarup Bhunia. 37-42 [doi]
• Pulsed-latch-based clock tree migration for dynamic power reductionHong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho. 39-44 [doi]
• Low-power sub-threshold design of secure physical unclonable functionsLang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne Burleson. 43-48 [doi]
• Matched public PUF: ultra low energy security platformSaro Meguerdichian, Miodrag Potkonjak. 45-50 [doi]
• Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systemsShahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum. 49-54 [doi]
• Pinned to the walls: impact of packaging and application properties on the memory and power wallsPhillip Stanley-Marbell, Victoria Caparrós Cabezas, Ronald P. Luijten. 51-56 [doi]
• 3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memoryYibo Chen, Jishen Zhao, Yuan Xie. 55-60 [doi]
• Designing ultra-low voltage logicTakayasu Sakurai. 57-58 [doi]
• Ultra-low-voltage operation: device perspectiveToshiro Hiramoto. 59-60 [doi]
• 3D super chip technology to achieve low-power and high-performance system-on-a chipMitsumasa Koyanagi. 61-62 [doi]
• Low-power current-mode transceiver for on-chip bidirectional busesMarshnil Vipin Dave, Rajkumar Satkuri, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 61-66 [doi]
• Holistic low power solutions for the new worldKee Sup Kim. 65-66 [doi]
• Low power branch prediction for embedded application processorsNadav Levison, Shlomo Weiss. 67-72 [doi]
• An energy-efficient adaptive hybrid cacheJason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou. 67-72 [doi]
• Reducing variability in chip-multiprocessors with adaptive body biasingAlyssa Bonnoit, Lawrence T. Pileggi. 73-78 [doi]
• Processor caches with multi-level spin-transfer torque ram cellsYiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh. 73-78 [doi]
• High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacementAmin Jadidi, Mohammad Arjomand, Hamid Sarbazi-Azad. 79-84 [doi]
• Diet SODA: a power-efficient processor for digital camerasSangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott A. Mahlke, Trevor N. Mudge. 79-84 [doi]
• TLB index-based tagging for cache energy reductionJongmin Lee, Seokin Hong, Soontae Kim. 85-90 [doi]
• Temperature- and energy-constrained scheduling in multitasking systems: a model checking approachWeixun Wang, Xiaoke Qin, Prabhat Mishra. 85-90 [doi]
• Versatile high-fidelity photovoltaic module emulation systemWoojoo Lee, Younghyun Kim, Yanzhi Wang, Naehyuck Chang, Massoud Pedram, Soohee Han. 91-96 [doi]
• A 6µw, 100kbps, 3-5ghz, UWB impulse radio transmitterRajeev K. Dokania, Xiao Y. Wang, Carlos I. Dorta-Quinones, Waclaw Godycki, Siddharth G. Tallur, Alyssa B. Apsel. 91-94 [doi]
• A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opampLeila Koushaeian, Stan Skafidas. 95-98 [doi]
• System energy minimization via joint optimization of the DC-DC converter and the coreRami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein. 97-102 [doi]
• A 5V output voltage boost switching converter with hybrid digital and analog PWM controlChien-Chun Lu, Ming-Ching Kuo. 99-104 [doi]
• Charge migration efficiency optimization in hybrid electrical energy storage (HEES) systemsYanzhi Wang, Younghyun Kim, Qing Xie, Naehyuck Chang, Massoud Pedram. 103-108 [doi]
• A low-power digitally-programmable variable gain amplifier in 65 nm CMOSAmir Zjajo, Mingxin Song. 105-110 [doi]
• Does low-power design imply energy efficiency for data centers?David Meisner, Thomas F. Wenisch. 109-114 [doi]
• PEEC based parasitic modeling for power analysis on custom rotary ringsVinayak Honkote, Baris Taskin. 111-116 [doi]
• Analysis of power-performance for ultra-thin-body GeOI logic circuitsVita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang. 115-120 [doi]
• HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offsGeorgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy. 117-122 [doi]
• Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan. 121-126 [doi]
• Analog circuit shielding routing algorithm based on net classificationQiang Gao, Yin Shen, Yici Cai, Hailong Yao. 123-128 [doi]
• Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscalingLei Jiang, Youtao Zhang, Jun Yang 0002. 127-132 [doi]
• MODEST: a model for energy estimation under spatio-temporal variabilityShrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio. 129-134 [doi]
• TG-based technique for NBTI degradation and leakage optimizationChin-Hung Lin, Ing-Chao Lin, Kuan-Hui Li. 133-138 [doi]
• Replication-aware leakage management in chip multiprocessors with private L2 cacheHyunhee Kim, Jung Ho Ahn, Jihong Kim. 135-140 [doi]
• Analysis and mitigation of NBTI-induced performance degradation for power-gated circuitsKai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang. 139-144 [doi]
• Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectivesHai Lin, Yunsi Fei. 141-146 [doi]
• Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMsDaeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester. 145-150 [doi]
• Energy efficient implementation of parallel CMOS multipliers with improved compressorsDursun Baran, Mustafa Aktan, Vojin G. Oklobdzija. 147-152 [doi]
• Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUsAlessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza. 151-156 [doi]
• Real-energy: a new framework and a case study to evaluate power-aware real-time scheduling algorithmsJian (Denny) Lin, Wei Song, Albert Mo Kim Cheng. 153-158 [doi]
• Design and analysis of metastable-hardened flip-flops in sub-threshold regionDavid Li, Pierce Chuang, David Nairn, Manoj Sachdev. 157-162 [doi]
• A low-power clock gating cell optimized for low-voltage operation in a 45-nm technologyMartin Saint-Laurent, Animesh Datta. 159-164 [doi]
• 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V::DD::) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V::DD:: between flip-flops and combinational logicsHiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. 163-168 [doi]
• Dynamic thermal management for single and multicore processors under soft thermal constraintsBing Shi, Yufu Zhang, Ankur Srivastava. 165-170 [doi]
• 8T single-ended sub-threshold SRAM with cross-point data-aware write operationYi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang. 169-174 [doi]
• A three-step power-gating turn-on technique for controlling ground bounce noiseRahul Singh, Ahreum Kim, Soyoung Kim, Suhwan Kim. 171-176 [doi]
• Reduction of minimum operating voltage (V::DDmin::) of CMOS logic circuits with post-fabrication automatically selective charge injectionKentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. 175-180 [doi]
• Customizing pattern set for test power reduction via improved X-identification and reorderingS. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay. 177-182 [doi]
• Eliminating energy of same-content-cell-columns of on-chip SRAM arraysBushra Ahsan, Lorena Ndreu, Isidoros Sideris, Sachin Idgunji, Emre Özer. 181-186 [doi]
• Analysis and design of ultra low power thermoelectric energy harvesting systemsChao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy. 183-188 [doi]
• A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOsAmir Zjajo, José Pineda de Gyvez. 187-192 [doi]
• RAPL: memory power estimation and cappingHoward David, Eugene Gorbatov, Ulf R. Hanebutte, Rahul Khanaa, Christian Le. 189-194 [doi]
• A low-power direct digital frequency synthesizer using an analogue-sine-conversion techniqueJun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu. 193-198 [doi]
• Energy efficient proactive thermal management in memory subsystemRaid Zuhair Ayoub, Krishnam Raju Indukuri, Tajana Simunic Rosing. 195-200 [doi]
• A comparator-based cyclic analog-to-digital converter with boosted preset voltageJong-Kwan Woo, Tae Hoon Kim, Hyongmin Lee, Sunkwon Kim, Hyunjoong Lee, Suhwan Kim. 199-204 [doi]
• Power-performance management on an IBM POWER7 serverKarthick Rajamani, Freeman L. Rawson III, Malcolm S. Ware, Heather Hanson, John Carter, Todd J. Rosedahl, Andrew J. Geissler, Guillermo Silva, Hong Hua. 201-206 [doi]
• Thermal-aware bus-driven floorplanningPo-Hsun Wu, Tsung-Yi Ho. 205-210 [doi]
• Energy and thermal-aware video coding via encoder/decoder workload balancingDomenic Forte, Ankur Srivastava. 207-212 [doi]
• An approach to energy-error tradeoffs in approximate ripple carry addersZvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem. 211-216 [doi]
• Tradeoff between energy savings and privacy protection in computation offloadingJibang Liu, Karthik Kumar, Yung-Hsiang Lu. 213-218 [doi]
• Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAsTaeko Matsunaga, Shinji Kimura, Yusuke Matsunaga. 217-222 [doi]
• 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAMYohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto. 219-224 [doi]
• New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHMCe Li, Yiping Dong, Takahiro Watanabe. 223-228 [doi]
• Workload-adaptive process tuning strategy for power-efficient multi-core processorsJungseob Lee, Chi-Chao Wang, Hamid Ghasemil, Lloyd Bircher, Yu Cao, Nam Sung Kim. 225-230 [doi]
• Learning to manage combined energy supply systemsAzalia Mirhoseini, Farinaz Koushanfar. 229-234 [doi]
• Small-area and low-energy ::::K::::-best MIMO detector using relaxed tree expansion and early forwardingTae-Hwan Kim, In-Cheol Park. 231-236 [doi]
• Energy harvesting by sweeping voltage-escalated charging of a reconfigurable supercapacitor arraySehwan Kim, Pai H. Chou. 235-240 [doi]
• Ultra low power electronics in the next decadeAjith Amerasekera. 237-238 [doi]
• Technology variability and uncertainty implications for power- efficient VLSI systemsKevin J. Nowka. 239-240 [doi]
• Workload-aware neuromorphic design of low-power supply voltage controllerSaurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao. 241-246 [doi]
• On-chip detection methodology for break-even time of power gated function unitsKimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura. 241-246 [doi]
• Distributed DVFS using rationally-related frequencies and discrete voltage levelsJean-Michel Chabloz, Ahmed Hemani. 247-252 [doi]
• Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicoresKarthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta. 247-252 [doi]
• Automated di/dt stressmark generation for microprocessor power delivery networksYoungtaek Kim, Lizy Kurian John. 253-258 [doi]
• NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetimeMehmet Basoglu, Michael Orshansky, Mattan Erez. 253-258 [doi]
• In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuitsNandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur. 259-264 [doi]
• A scheduling algorithm for consistent monitoring results with solar powered high-performance wireless embedded systemsDenis Dondi, Piero Zappi, Tajana Simunic Rosing. 259-264 [doi]
• Leakage minimization using self sensing and thermal managementAlireza Vahdatpour, Miodrag Potkonjak. 265-270 [doi]
• A design space exploration of transmission-line links for on-chip interconnectAaron Carpenter, Jianyun Hu, Michael C. Huang, Hui Wu, Peng Liu. 265-270 [doi]
• Clock network design for ultra-low power applicationsMingoo Seok, David Blaauw, Dennis Sylvester. 271-276 [doi]
• An integrated optimization framework for reducing the energy consumption of embedded real-time applicationsHideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada. 271-276 [doi]
• Memory energy management for an enterprise decision support systemKarthik Kumar, Kshitij Doshi, Martin Dimitrov, Yung-Hsiang Lu. 277-282 [doi]
• Large-scale battery system modeling and analysis for emerging electric-drive vehiclesKun Li, Jie Wu, Yifei Jiang, Zyad Hassan, Qin Lv, Li Shang, Dragan Maksimovic. 277-282 [doi]
• Power-efficient directional wireless communication on small form-factor mobile devicesArdalan Amiri Sani, Hasan Dumanli, Lin Zhong, Ashutosh Sabharwal. 283-288 [doi]
• The whys and hows of thermal managementSachin S. Sapatnekar. 283-284 [doi]
• A dynamic body-biased SRAM with asymmetric halo implant MOSFETsMakoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii. 285-290 [doi]
• Dynamic thermal management for networked embedded systems under harsh ambient temperature variationSangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang. 289-294 [doi]
• A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOSMing-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang. 291-296 [doi]
• PS-BC: power-saving considerations in design of buffer caches serving heterogeneous storage devicesFeng Chen, Xiaodong Zhang. 295-300 [doi]
• An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signalJoseph F. Ryan, Sudhanshu Khanna, Benton H. Calhoun. 297-302 [doi]
• Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detectionHimanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy. 301-306 [doi]
• Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processorsSang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy. 303-308 [doi]
• Maximum power transfer tracking for a photovoltaic-supercapacitor energy systemYounghyun Kim, Naehyuck Chang, Yanzhi Wang, Massoud Pedram. 307-312 [doi]
• Dynamic backlight scaling optimization for mobile streaming applicationsPi-Cheng Hsiu, Chun-Han Lin, Cheng-Kang Hsieh. 309-314 [doi]
• DuraCap: a supercapacitor-based, power-bootstrapping, maximum power point tracking energy-harvesting systemChien-Ying Chen, Pai H. Chou. 313-318 [doi]
• Object-based local dimming for LCD systems with LED BLUsAldhino Anggorosesar, Young-Jin Kim. 315-320 [doi]
• Peak power modeling for data center servers with switched-mode power suppliesDavid Meisner, Thomas F. Wenisch. 319-324 [doi]
• OS-level power minimization under tight performance constraints in general purpose systemsRaid Zuhair Ayoub, Ümit Y. Ogras, Eugene Gorbatov, Yanqin Jin, Timothy Kam, Paul Diefenbaugh, Tajana Rosing. 321-326 [doi]
• Load-matching adaptive task scheduling for energy efficiency in energy harvesting real-time embedded systemsShaobo Liu, Jun Lu, Qing Wu, Qinru Qiu. 325-330 [doi]
• Energy efficient scheduling for multithreaded programs on general-purpose processorsXin Fan, Shigeru Kusakabe. 327-332 [doi]
• Post-silicon power characterization using thermal infrared emissionsRyan Cochran, Abdullah Nazma Nowroz, Sherief Reda. 331-336 [doi]
• Software energy estimation based on statistical characterization of intermediate compilation codeCarlo Brandolese, Simone Corbetta, William Fornaciari. 333-338 [doi]
• Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternativesRouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif. 337-342 [doi]
• Energy efficient E-textile based portable keyboardMahsan Rofouei, Miodrag Potkonjak, Majid Sarrafzadeh. 339-344 [doi]
• Dynamic indexing: concurrent leakage and aging optimization for cachesAndrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino. 343-348 [doi]
• A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applicationsSunkwon Kim, Jong-Kwan Woo, Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Hyunjoong Lee, Suhwan Kim. 347-350 [doi]
• Low power logic for statistical inferenceBenjamin Vigoda, David Reynolds, Jeffrey Bernstein, Theophane Weber, Bill Bradley. 349-354 [doi]
• A 92.4dB SNDR 24kHz ΔΕ modulator consuming 352μWLiyuan Liu, Dongmei Li, Yafei Ye, Zhihua Wang. 351-356 [doi]
• Resilient microprocessor design for high performance & energy efficiencyKeith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De. 355-356 [doi]
• Computing with stochastic processors: revisiting the correctness contract between software and hardwareRakesh Kumar. 357-358 [doi]
• A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array systemHyunjoong Lee, Hyongmin Lee, Jong-Kwan Woo, Sunkwon Kim, Young-June Park, Suhwan Kim. 357-360 [doi]
• Models for energy-efficient approximate computingRavi Nair. 359-360 [doi]
• Battery management technology for an electric vehicleJeff Lee. 361-362 [doi]
• Hybrid electrical energy storage systemsMassoud Pedram, Naehyuck Chang, Younghyun Kim, Yanzhi Wang. 363-368 [doi]
• Green high performance storage class memory & NAND flash memory hybrid SSD systemKen Takeuchi. 369-370 [doi]
• Hybrid energy storage system integration for vehiclesJia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang. 369-374 [doi]
• ::::The K computer::::: Japanese next-generation supercomputer development projectMitsuo Yokokawa, Fumiyoshi Shoji, Atsuya Uno, Motoyoshi Kurokawa, Tadashi Watanabe. 371-372 [doi]
• A 98 GMACs/W 32-core vector processor in 65nm CMOSXun He, Dajiang Zhou, Xin Jin, Satoshi Goto. 373-378 [doi]
• TurboTag: lookup filtering to reduce coherence directory powerPejman Lotfi-Kamran, Michael Ferdman, Daniel Crisan, Babak Falsafi. 377-382 [doi]
• Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systemsQiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González. 379-384 [doi]
• Rank-aware cache replacement and write buffering to improve DRAM energy efficiencyAhmed M. Amin, Zeshan Chishti. 383-388 [doi]
• Fast and energy-efficient constant-coefficient FIR filters using residue number systemPiotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava. 385-390 [doi]
• An energy efficient cache design using spin torque transfer (STT) RAMMitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili. 389-394 [doi]
• A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systemsJunyoung Park, Jacob A. Abraham. 391-396 [doi]
• PASAP: power aware structured ASIC placementAshutosh Chakraborty, David Z. Pan. 395-400 [doi]
• Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designsYibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie. 397-402 [doi]
• Automatic synthesis of near-threshold circuits with fine-grained performance tunabilityMohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini. 401-406 [doi]
• NoC frequency scaling with flexible-pipeline routersPingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar. 403-408 [doi]
• A pareto-algebraic framework for signal power optimization in global routingHamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten. 407-412 [doi]
• IMPACT: imprecise adders for low-power approximate computingVaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy. 409-414 [doi]
• Wakeup synthesis and its buffered tree construction for power gating circuit designsSeungwhun Paik, Sangmin Kim, Youngsoo Shin. 413-418 [doi]
• Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessorsJaehyun Park, Donghwa Shin, Naehyuck Chang, Massoud Pedram. 419-424 [doi]
• Custom feedback control: enabling truly scalable on-chip power management for MPSoCsSiddharth Garg, Diana Marculescu, Radu Marculescu. 425-430 [doi]
• STM versus lock-based systems: an energy consumption perspectiveFelipe Klein, Alexandro Baldassin, Joao Moreira, Paulo Centoducatte, Sandro Rigo, Rodolfo Azevedo. 431-436 [doi]
• Dynamic workload characterization for power efficient scheduling on CMP systemsGaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew. 437-442 [doi]