Yiping Dong - researchr alias

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Viewing Publication 1 - 16 from 16

2025

ARTimeTravel: Understanding Spatial Changes in Heritage Sites Over Time through Web-Based Augmented Reality Serious GamesJiachen Liang, Gengyuan Zeng, Yue Li 0023, Yiping Dong. CHI 2025: [doi]

2024

HeritageSite AR: Design and Evaluation of a Mobile Augmented Reality Exploration Game for a Chinese Heritage SiteNingning Xu, Yue Li 0023, Jiachen Liang, Kexiang Shuai, Yuwen Li, Jiaqi Yan, Cheng Zhang 0015, Yiping Dong. jocch, 17(4), December 2024. [doi]

2022

Integrated Navigation on Vehicle Based on Low-cost SINS/GNSS Using Deep LearningNing Liu 0011, Hui Zhao 0008, Zhong Su, Likang Qiao, Yiping Dong. wpc, 126(3):2043-2064, 2022. [doi]

DPMPC-Planner: A real-time UAV trajectory planning framework for complex static environments with dynamic obstaclesZhefan Xu, Di Deng, Yiping Dong, Kenji Shimada. icra 2022: 250-256 [doi]

2020

2019

Identification of a Five-CpG Signature with Diagnostic Value in Thyroid CancerXi Jia, Qian Zhao, Yuanyuan Zhang, Yiping Dong, Li Lei, Ramone A. Williamson, Yutiantian Lei, Xinyue Tan, Dan Zhang, Jinsong Hu. jcb, 26(12):1409-1417, 2019. [doi]

2018

Integrated Bioinformatics Analysis for Identificating the Therapeutic Targets of Aspirin in Small Cell Lung CancerLiuyun Gong, Dan Zhang, Yiping Dong, Yutiantian Lei, Yuanjie Qian, Xinyue Tan, Suxia Han, Jiquan Wang. jbi, 88:20-28, 2018. [doi]

2012

Region Oriented Routing FPGA Architecture for Dynamic Power GatingCe Li, Yiping Dong, Takahiro Watanabe. ieicet, 95-A(12):2199-2207, 2012. [doi]

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA ArchitectureCe Li, Yiping Dong, Takahiro Watanabe. ieicet, 95-D(2):314-323, 2012. [doi]

2011

New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHMCe Li, Yiping Dong, Takahiro Watanabe. islped 2010: 223-228 [doi]

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA ArchitectureCe Li, Yiping Dong, Takahiro Watanabe. ieicet, 94-A(12):2519-2527, 2011. [doi]

2010

High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channelsYiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe. iscas 2010: 381-384 [doi]

A hybrid architecture for efficient FPGA-based implementation of multilayer neural networkZhen Lin, Yiping Dong, Yan Li, Takahiro Watanabe. apccas 2010: 616-619 [doi]

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