Abstract is missing.
- A novel statistical and circuit-based technique for counterfeit detection in existing ICsRashmi Moudgil, Dinesh Ganta, Leyla Nazhandali, Michael Hsiao, Chao Wang, Simin Hall. 1-6 [doi]
- Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAsCinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone. 7-12 [doi]
- A novel intermittent fault Markov model for deep sub-micron processorsBabak Saghaie, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic. 13-18 [doi]
- High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policyShun-Ming Syu, Yu-Hui Shao, Ing-Chao Lin. 19-24 [doi]
- Harvesting-aware energy management for multicore platforms with hybrid energy storageYi Xiang, Sudeep Pasricha. 25-30 [doi]
- Early stage power management for 3D FPGAs considering hierarchical routing resourcesKrishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki Murakami. 31-36 [doi]
- A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm nodePablo Royer, Marisa López-Vallejo. 37-42 [doi]
- Virtual register renaming: energy efficient substrate for continual flow pipelinesKomal Jothi, Haitham Akkary. 43-48 [doi]
- Skew-bounded low swing clock tree optimizationCan Sitik, Baris Taskin. 49-54 [doi]
- Coordinating prefetching and STT-RAM based last-level cache management for multicore systemsMengjie Mao, Hai Helen Li, Alex K. Jones, Yiran Chen. 55-60 [doi]
- Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and aboveQing Xie, Yanzhi Wang, Massoud Pedram. 61-66 [doi]
- An energy-efficient truly all-digital temperature sensor for SoC applicationsTzu-Yuan Kuo, Keng-Jui Chang, Jen-Hsiang Lee, Zong-Wu He, Jinn-Shyan Wang. 67-70 [doi]
- Efficient characterization of TSV-to-transistor noise coupling in 3D ICsHailang Wang, Mohammad H. Asgari, Emre Salman. 71-76 [doi]
- A portable high-frequency digitally controlled oscillator (DCO)Muhammad E. S. Elrabaa. 77-82 [doi]
- A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOSJaeyoung Kim, Kwen-Siong Chong, Joseph Sylvester Chang, Pinaki Mazumder. 83-88 [doi]
- GPU implementation of a scalable non-linear congruential generator for cryptography applicationsAditya Belsare, Steve Liu, Sunil Khatri. 89-94 [doi]
- Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysisTakumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 95-100 [doi]
- Translation validation of scheduling in high level synthesisTun Li, Yang Guo, Wanwei Liu, Mingsheng Tang. 101-106 [doi]
- LASER: layout-aware analog synthesis environment on lakerYu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen. 107-112 [doi]
- Hardware acceleration of retinal blood vasculature segmentationDimitris Koukounis, Christos Ttofis, Theocharis Theocharides. 113-118 [doi]
- A 191μW BPSK demodulator for data and power telemetry in biomedical implantsLi-Lan Wang, Chia-Hsiang Yang, Herming Chiueh. 119-124 [doi]
- Custom memory architecture for multi-core implementation of face detection algorithmDavid Watson, Ali Ahmadinia, Gordon Morison, Tom Buggy. 125-130 [doi]
- A novel and improved design of a ternary CNTFET-based cellGeunho Cho, Fabrizio Lombardi. 131-136 [doi]
- Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuitsArne Heittmann, Tobias G. Noll. 137-142 [doi]
- Asymmetric-access aware optimization for STT-RAM caches with process variationsYi Zhou, Chao Zhang, Guangyu Sun, Kun Wang, Yu Zhang. 143-148 [doi]
- A new extension method of retention time for memory cell on dynamic random access memoryYoshiro Riho, Kazuo Nakazato. 149-154 [doi]
- A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardwareAbdulkadir Akin, Ipek Baz, Baris Atakan, Irem Boybat, Alexandre Schmid, Yusuf Leblebici. 155-160 [doi]
- A source-synchronous Htree-based network-on-chipAyan Mandal, Sunil P. Khatri, Rabi N. Mahapatra. 161-166 [doi]
- A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detectionUwe Deidersen, Dominik Auras, Gerd Ascheid. 167-172 [doi]
- Scaling RTL property checking using feasible path analysisand decompositionLingyi Liu, Shobha Vasudevan. 173-178 [doi]
- SIREN: a depth-first search algorithm for the filter design optimization problemLevent Aksoy, Paulo F. Flores, José Monteiro. 179-184 [doi]
- Generating concise assertions with complete coverageChen-Hsuan Lin, Lingyi Liu, Shobha Vasudevan. 185-190 [doi]
- Efficient transistor-level design of CMOS gatesVinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Junior. 191-196 [doi]
- Electronics for a greener planetChristian Piguet. 197-202 [doi]
- Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsJin-Tai Yan, Zhi-Wei Chen. 203-208 [doi]
- Multi-corner multi-voltage domain clock mesh designCan Sitik, Baris Taskin. 209-214 [doi]
- Combating NBTI-induced aging in data cachesShuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin. 215-220 [doi]
- Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional unitsSimone Corbetta, William Fornaciari. 221-226 [doi]
- Delay model for reconfigurable logic gates based on graphene PN-junctionsSandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino. 227-232 [doi]
- Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arraysQin Wang, Arne Heittmann, Tobias G. Noll. 233-238 [doi]
- DRMA: dynamically reconfigurable MPSoC architectureLawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja. 239-244 [doi]
- A compact FPGA-based montgomery multiplier over prime fieldsMiguel Morales-Sandoval, Arturo Diaz-Perez. 245-250 [doi]
- n-1 cubing unitsEvangelos Vassalos, Dimitris Bakalis. 251-256 [doi]
- An error tolerant CAM with nand match-line organizationAristides Efthymiou. 257-262 [doi]
- n+1 multiplication for the idea block cipherKiamal Z. Pekmestzi, Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis. 263-268 [doi]
- An asymmetric adaptive-precision energy-efficient 3DIC multiplierNeela Gopi, Jeffrey Draper. 269-274 [doi]
- Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICsCaleb Serafy, Bing Shi, Ankur Srivastava. 275-280 [doi]
- Thermal stress aware 3D-IC statistical static timing analysisBing Shi, Ankur Srivastava. 281-286 [doi]
- Effect of TSV fabrication technology on power distribution in 3D ICsSuhas M. Satheesh, Emre Salman. 287-292 [doi]
- Multi-port FinFET SRAM designYirong Zhao, Jiayin Li, Kartik Mohanram. 293-298 [doi]
- Modeling symmetrical independent gate FinFET using predictive technology modelMohammad Yousef Zarei, Reza Asadpour, Siamak Mohammadi, Ali Afzali-Kusha, Razi Seyyedi. 299-304 [doi]
- A self-tuning multi-objective optimization framework for geometric programming with gate sizing applicationsAmin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick. 305-310 [doi]
- Low power 3-D stacking multimedia platform with reconfigurable memory architecturePo-Han Huang, Huang-Lun Lin, Hsien-Ching Hsieh, Chi-Hung Lin, Shui-An Wen, Yi-Fa Sun. 311-312 [doi]
- High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici. 313-314 [doi]
- A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithmGong Chen, Bo Yang 0004, Yu Zhang, Qing Dong, Shigetoshi Nakatake. 315-316 [doi]
- An evaluation of an AES implementation protected against EM analysisPaolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle. 317-318 [doi]
- PBD: packet buffer DVFsEyal-Itzhak Nave, Ran Ginosar. 319-320 [doi]
- A memory mapping approach for network and controller optimization in parallel interleaver architecturesAroua Briki, Cyrille Chavet, Philippe Coussy. 321-322 [doi]
- Post-route refinement for high-frequency PCBs considering meander segment alleviationTsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. 323-324 [doi]
- On-chip area-efficient binary sequence storageNan Li, Elena Dubrova. 325-326 [doi]
- Power gating topologies in TSV based 3D integrated circuitsHailang Wang, Emre Salman. 327-328 [doi]
- Architecture and 3D device simulation of a PIN diode-based Gamma radiation detectorAmr Elshennawy, Craig M. Marianno, Sunil P. Khatri. 329-330 [doi]
- Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstractMahmoud Elbayoumi, Michael S. Hsiao, Mustafa Y. ElNainay. 331-332 [doi]
- Circuit design of a novel adaptable and reliable L1 data cacheAzam Seyedi, Gulay Yalcin, Osman S. Unsal, Adrián Cristal. 333-334 [doi]
- Physical design exploration of 3D tree-based FPGA architectureVinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi. 335-336 [doi]
- Co-optimization of TSV assignment and micro-channel placement for 3D-ICsBing Shi, Caleb Serafy, Ankur Srivastava. 337-338 [doi]
- Lifetime reliability assessment with aging information from low-level sensorsYao Wang, Sorin Dan Cotofana, Liang Fang. 339-340 [doi]
- A hardware-efficient architecture for embedded real-time cascaded support vector machines classificationChristos Kyrkou, Theocharis Theocharides, Christos-Savvas Bouganis. 341-342 [doi]
- Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resourcesYazhuo Dong, Wu Zhan, Xiqing Ye. 343-344 [doi]
- Study of ASIC technology impact factors on performance evaluation of SHA-3 candidatesMeeta Srivastav, Yongbo Zuo, Xu Guo, Leyla Nazhandali, Patrick Schaumont. 345-346 [doi]
- Timing-constrained replacement using spare cells for design changesZhi-Wei Chen, Jin-Tai Yan. 347-348 [doi]
- Rotary traveling wave oscillator frequency division at nanoscale technologiesYing Teng, Baris Taskin. 349-350 [doi]
- Reversible synthesis of symmetric boolean functions based on unate decompositionArighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya. 351-352 [doi]