Abstract is missing.
- The circuit paradigm in nanoelectronics - field-coupled and hybrid nanoelectronic circuitsÁrpád I. Csurgay, Wolfgang Porod, Stephen M. Goodnick. 1-6 [doi]
- Plenary lecture [Second page is a blank]Alfred Fettweis. 1-2 [doi]
- Plenary lecture [Second page is blank]Giovanni De Micheli. 1-2 [doi]
- Neural network simulator for circuit modeling and analysis based on fast automatic differentiationGanesh Kumar Basnet, Masayuki Yamauchi, Mamoru Tanaka. 3-6 [doi]
- Stability of the quasi-periodic and periodic attractors constrained to the hyper-plane in a ring of three-coupled hard-type oscillatorsKuniyasu Shimizu, Tetsuro Endo. 3-6 [doi]
- Realization of limit cycles by neural networks with piecewise linear activation functionNorikazu Takahashi, Tsuyoshi Yamakawa, Tetsuo Nishi. 7-10 [doi]
- A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuitAlon Ascoli, Paul F. Curran, Orla Feely. 7-10 [doi]
- Bifurcation analysis in a hybrid time delay systemTakuji Kousaka, Yue Ma. 7-10 [doi]
- Artificial immune systems based sound event detection with CNN-UMJasper Stolte, György Cserey. 11-14 [doi]
- One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/sourceTomoumi Yagasaki, Yoshihiko Horio, Kazuyuki Aihara. 11-14 [doi]
- Non-linear dynamics in servo positioning loopsPedro Ramírez, Andrés Guesalaga. 11-14 [doi]
- On phase pattern transition in star-coupled Wien-bridge oscillators with parameter deviationsSeiichiro Moro, Tadashi Matsumoro. 15-18 [doi]
- An improved, very long time-constant CMOS integrator for use in implantable neuroprosthetic devicesIasonas F. Triantis, Andreas Demosthenous. 15-18 [doi]
- DC and AC characteristics and modeling of Si SSD-nano devicesMarkku Åberg, Jan Saijets. 15-18 [doi]
- Generation of balanced biphasic stimulus current with integrated blocking capacitorXiao Liu 0001, Andreas Demosthenous. 19-22 [doi]
- Conditional quasi maximum-likelihood receiver for clipped OFDM signalsSebastian Prot, Mark Flanagan, Conor Heneghan. 19-22 [doi]
- Oscillators and operational amplifiersErik Lindberg. 19-22 [doi]
- On the usage of delayed-feedback in amplifiersLuis Nero Alves, Rui L. Aguiar. 23-26 [doi]
- Theoretical investigation of the stability of the modes in an array of coupled oscillators for linear and circular arrangementsAli Banai, Forouhar Farzaneh. 23-26 [doi]
- Design of a bioimpedance measurement system using direct carrier compensationPaul Annus, Jürgen Lamp, Mart Min, Toivo Paavle. 23-26 [doi]
- 2-V CMOS current operational amplifier with high CMRRRaimondo Luzzi, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti. 27-30 [doi]
- A novel CMOS temperature control system for resistive gas sensor arraysGiuseppe Ferri, Nicola Carlo Guerrini, Vincenzo Stornelli, Carlo Catalani. 27-32 [doi]
- Multiphase active-RC sinusoidal oscillators incorporating lowpass and allpass sectionsJohn Vosper, Richard Deloughry, Brett Wilson. 27-30 [doi]
- A design scheme for sampling switch in active matrix LCDShingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa. 31-34 [doi]
- A complete front-end system read-out and temperature control for resistive gas sensor arrayMattia Malfatti, Matteo Perenzoni, Nicola Viarani, Andrea Simoni, Leandro Lorenzelli, Andrea Baschirotto. 31-34 [doi]
- Rail-to-rail OTA utilizing linear V-I conversion circuit using single channel MOSFETs for input stageNobukazu Takai, Shinji Nomura. 31-34 [doi]
- A theoretical discussion on performance limits of CMOS charge pumpsAlessandro Cabrini, Laura Gobbi, Guido Torelli. 35-38 [doi]
- A miniaturised modular platform for wireless sensor networksJohn Barton, Brendan O'Flynn, Stephen J. Bellis, Andrew Lynch, Michael Morris, Seán Cian O'Mathuna. 35-38 [doi]
- 1.8 V.0.35 μm CMOS wideband programmable gain amplifierBelén Calvo, Santiago Celma, Pedro A. Martínez, Maria Teresa Sanz. 35-38 [doi]
- Analysis of diode-transistor circuits having multiple DC solutionsMichal Tadeusiewicz, Stanislaw Halgas. 39-42 [doi]
- Analysis of coil parameter extraction methods for on-chip inductor designAlkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs. 39-42 [doi]
- Nonlinear effects of RF interference in SC circuitsPaolo Stefano Crovetti, Franco L. Fiori. 39-42 [doi]
- Partitioning large circuits to speed up numerical simulationsAngelo Brambilla, Giancarlo Storti Gajani, Amedeo Premoli. 43-46 [doi]
- New admittance matrix descriptions for the nullor with application to circuit designDavid G. Haigh, Paul M. Radmore. 43-46 [doi]
- Simulation of ferrites by SPICEJacek Izydorczyk. 43-46 [doi]
- A methodology for fast reuse of analog circuit schematicsPedro C. Ventura, Marco Oliveira. 47-50 [doi]
- Geometrical analysis of two-transistor circuits with more than three operating pointsMartin Claus. 47-50 [doi]
- Compact model for a cantilever beam MEM contact switchTimo Veijola. 47-50 [doi]
- Novel autonomous current mode one-cycle controller for PFC AC-DC pre-regulatorsAbdelali El Aroudi, Roberto Giral, Javier Maixe-Altes, Javier Calvente, Luis Martínez-Salamero. 51-54 [doi]
- Efficient algorithms for the computation and application of Volterra kernels in the behavior analysis of nonlinear circuits and systemsAndreas Bauer. 51-54 [doi]
- Band-pass hybrid filter bank A/D converters with software-controlled bandwidth and resolutionCaroline Lelandais-Perrault, Daniel Poulton, Jacques Oksman. 51-54 [doi]
- Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCsOlujide A. Adeniran, Andreas Demosthenous. 55-58 [doi]
- Sliding mode control of a high voltage DC-DC buck converterAbdelali El Aroudi, Bruno Robert, Ramon Leyva. 55-60 [doi]
- A yield-enhancement strategy for binary-weighted DACsK. Ola Andersson, Mark Vesterbacka. 55-58 [doi]
- Modeling finite-memory nonlinearity in unit DAC elements, binary storage channels, and BPSK data channelsJeffrey O. Coleman. 59-62 [doi]
- Linearity enhancement of oversampled pipeline A/D converters using sigma-delta modulationJosé L. Ausín, Guido Torelli, J. Francisco Duque-Carrillo. 59-62 [doi]
- Blind source separation for improved load forecasting in the power systemKrzysztof Siwek, Stanislaw Osowski, Ryszard Szupiluk, Piotr Wojewnik, Tomasz Zabkowski. 61-64 [doi]
- Dithered subband coding with spectral subtractionChatree Budsabathon, Akinori Nishihara. 63-66 [doi]
- A 2.0-V folding circuit using current limiting amplifier for ADCTakeshi Koike, Akira Hyogo, Keitaro Sekine. 63-66 [doi]
- An investigation of coded OFDM and OFDM-CDMA waveforms utilizing different modulation schemes on HF multipath/fading channelsJohn W. Nieto. 65-68 [doi]
- Constrained ICA for functional magnetic resonance imagingMarco Balsi, Giuseppe Filosa, Giancarlo Valente, Patrizia Pantano. 67-70 [doi]
- A Gradient-based adaptive algorithm for minimum phase-all pass decomposition of an FIR systemMark F. Flanagan, Anthony D. Fagan. 67-70 [doi]
- System requirements for OFDM polar transmitterMikko Talonen, Saska Lindfors. 69-72 [doi]
- Towards a hardware realization of time-frequency source separation of speechNaomi Harte, Niall P. Hurley, Conor Fearon, Scott Rickard. 71-74 [doi]
- Lossless video coding using bi-directional 3D prediction optimized for each frameIchiro Matsuda, Taichiro Shiodera, Hiroki Maeda, Susumu Itoh. 71-74 [doi]
- Quality improvement of bone-conducted speechTetsuya Shimamura, Takeshi Tomikura. 73-76 [doi]
- Time division digital programmable OTA for cellular neural networksFausto Sargeni, Vincenzo Bonaiuto, Maurizio Bonifazi. 75-78 [doi]
- Feature space derivation for isolated utterance reading with discriminant deformable modelsKrzysztof Slot, Hubert Nowak. 75-78 [doi]
- Tracking for a CNN guided robotGiovanni Egidio Pazienza, Pasqualino Giangrossi, Sebastià Tortella, Marco Balsi, Xavier Vilasís-Cardona. 77-80 [doi]
- Inverse elastic wave propagation modeling on CNN-UM architectureP. Sonkoly, Sándor Kocsárdi, P. Kozma, Péter Szolgay. 79-82 [doi]
- UWB technology: chaotic communications versus noncoherent impulse radioGéza Kolumbán. 79-82 [doi]
- Architecture of asynchronous cellular processor array for image skeletonizationAliaksei Lopich, Piotr Dudek. 81-84 [doi]
- A customizable tool for cellular nonlinear network simulationMario Salerno, Daniele Casali, Giovanni Costantini, Massimo Carota. 83-86 [doi]
- A fast and simple implementation of Chua's oscillator using a "cubic-like" Chua diodeKeith O'Donoghue, Michael Peter Kennedy, Peadar Forbes. 83-86 [doi]
- Image processing using periodic pattern formation in cellular neural networksTaisuke Nishio, Yoshifumi Nishio. 85-88 [doi]
- An area and power efficient discrete-time chaos generator circuitPiotr Dudek, V. D. Juncu. 87-90 [doi]
- A 1.9 GHz CMOS class E power amplifier with +29 dBm output power and 58% PAEShadi Tawfik, Tian Tong, Troels Studsgaard Nielsen, Torben Larsen. 87-90 [doi]
- DS model fitted using harmonic-balance simulationJanne P. Aikio, Timo Rahkonen. 89-92 [doi]
- A 1.5V 150MS/s current-mode sample-and-hold circuitBehnam Sedighi, Hold Omid Rajaee, Amin Jahanian, Mehrdad Sharif Bakhtiar. 91-94 [doi]
- Design of a novel type of on-chip transformer suitable for baluns in customary BICMOS/CMOS technologiesShashikanth Bobba, Ashoka S. V., Thomas Mattsson, Stefan Nilsson. 91-94 [doi]
- Distortion analysis of three-stage amplifiers with reversed nested-Miller compensationSalvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi. 93-96 [doi]
- A 1.5V 60MS/s sampled-data filter in 0.18μm CMOSBehnam Sedighi, Mehrdad Sharif Bakhtiar. 95-98 [doi]
- A reconfigurable CMOS VCO with an automatic amplitude controller for multi-band RF front-endsAli Fard, Denny Åberg. 95-98 [doi]
- New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiersSalvatore Omar Cannizzaro, Gaetano Palumbo, Salvatore Pennisi. 97-100 [doi]
- A high-speed sense-amplifier based flip-flopD. DeCaro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo. 99-102 [doi]
- Improving capacitive drive capability of two-stage op amps with current bufferMikko Loikkanen, Juha Kostamovaara. 99-102 [doi]
- Explicit design equations for class-E power amplifiers with small DC-feed inductanceDusan M. Milosevic, Johan van der Tang, Arthur H. M. van Roermund. 101-104 [doi]
- Design of high-performance tunable filters based on current conveyorsAntonio J. López-Martín, Jaime Ramírez-Angulo, Ramón González Carvajal. 103-106 [doi]
- Integrated low noise preamplifier for biologic-electronics interfacesEmanuele Bottino, Maurizio Valle. 103-106 [doi]
- Design of class E amplifier with any output Q and nonlinear capacitance on MOSFETHiroo Sekiya, Yoji Arifuku, Hiroyuki Hase, Jianming Lu, Takashi Yahagi. 105-108 [doi]
- Minimization of offset of the tunable LP filtersKarel Hajek, Jirí Sedlácek, Bohumir Sviezeny. 107-110 [doi]
- Switched current filter design with the use of integrators composed of equal size transistorsAndrzej Handkiewicz, Radoslaw Rudnicki, Marek Kropidlowski. 107-110 [doi]
- Guidelines for designing class-AB output stagesWalter Aloisi, Gianluca Giustolisi, Gaetano Palumbo. 109-112 [doi]
- A behavioral model for the nonlinear on-resistance in sample-and-hold analog switchesWilliam Prodanov, Maurizio Valle. 111-114 [doi]
- A class AB 6th order log-domain filter in BiCMOS with 100-500 MHz tuning rangeKlaus Schmalz, Mykhaylo A. Teplechuk, John I. Sewell. 111-114 [doi]
- General solution of linear differential equations by using differential transfer matrix methodMohammad Hadi Eghlidi, Khashayar Mehrany, Bizhan Rashidian. 113-116 [doi]
- Systematic synthesis of operational amplifier circuits by admittance matrix expansionDavid G. Haigh. 115-118 [doi]
- A simple submicron MOSFET model and its application to the analytical characterization of analog circuitsM. Helena Fino. 115-118 [doi]
- On the transfer matrix synthesis of two-dimensional orthogonal systemsMarian S. Piekarski, Robert T. Wirski. 117-120 [doi]
- Performance estimator for an analog design automation system using EKV-modeled analog circuitsEngin Deniz, Günhan Dündar. 119-122 [doi]
- Comparative study of MOST resistive configurationsJuan Pablo Alegre, Santiago Celma, Maria Teresa Sanz, Belén Calvo. 119-122 [doi]
- Frequency adjusting numerical technique for oscillator simulationMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney, Kiran K. Gullapalli. 121-124 [doi]
- An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction techniqueYujin Park, Sanghoon Hwang, Minkyu Song. 123-126 [doi]
- A project based master's programme for SoF/SoC based sensor systemsMattias O'Nils, Bengt Oelmann, Kent Bertilsson, Hans-Erik Nilsson, Göran Thungström. 123-126 [doi]
- Output power control in a power combiner with class-DE amplifiersJuliusz Modzelewski, Miroslaw Mikolajewski. 125-128 [doi]
- Prediction of Coulomb blockade in arbitrary environmentsJaap Hoekstra. 127-130 [doi]
- 6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applicationsErik Sall, Mark Vesterbacka. 127-130 [doi]
- Study of parasitic and stray components induced ringings in class E power amplifiers in MHz rangeHao Zhang, Siu Chung Wong, Chi K. Tse, Xikui Ma. 129-132 [doi]
- Design techniques for high performance CMOS flash analog-to-digital convertersSunghyun Park, Michael P. Flynn. 131-134 [doi]
- Hall-effect circuits and architectures for non-volatile system designNicholas P. Carter, Steve Ferrera, Love Kothari, Stanley Ye. 131-134 [doi]
- Optimization procedure of class E amplifiers using SPICEYuichi Tanji, Hiroo Sekiya, Hideki Asai. 133-136 [doi]
- New logic circuits consisting of quantum dots and CMOSWoo Hyung Lee, Pinaki Mazumder. 135-138 [doi]
- Robust reconstruction of nonuniformly sampled signalsJoachim F. Selinger, Axel Wenzler. 135-138 [doi]
- Beamforming system for 3G and 4G wireless LAN applicationsDora Lee, Wai Tung Ng. 137-140 [doi]
- Computing minimum-phase factors of polynomialsYuri Dolgin, Ezra Zeheb. 139-142 [doi]
- Efficient sine and cosine computation using a weighted sum of bit-productsLars Wanhammar, Kenny Johansson, Oscar Gustafsson. 139-142 [doi]
- 2 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aidsFlavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. 141-144 [doi]
- Fixed-point implementation of a robust complex valued divider architectureFredrik Edman, Viktor Öwall. 143-146 [doi]
- n - 1 multiplication/sum-of-squares unitsD. Adamidis, Haridimos T. Vergos. 143-146 [doi]
- A downlink beamforming in consideration of common pilot and phase mismatchByungjin Chun. 145-148 [doi]
- Plenary lecture [Second page is blank]Ivo Bolsens. 147-148 [doi]
- Argument principle and discrete Fourier transformCorneliu Rusu, Jaakko Astola. 147-150 [doi]
- Per-pixel integration time controlled image sensorÁkos Zarándy, Péter Földesy, Tamás Roska. 149-152 [doi]
- Robustness improvement in binary cellular non-linear network architecturesVictor M. Brea, Mika Laiho, Ari Paasio. 149-152 [doi]
- Plenary lecture [Second page is a blank]Leon O. Chua. 151-152 [doi]
- A simple variable λ resistive network implementationAsko Kananen, Ari Paasio, Kari Halonen. 153-156 [doi]
- Lyapunov exponent of EEG signal for epileptic seizure characterizationBartosz Swiderski, Stanislaw Osowski, Andrzej Rysz. 153-156 [doi]
- On cellular neural network learningXavier Vilasís-Cardona, Mireia Vinyoles-Serra. 153-156 [doi]
- Study of nonlinear dynamics of LDPC decodersXia Zheng, Francis C. M. Lau 0002, Chi K. Tse, Siu Chung Wong. 157-160 [doi]
- A new CNN template for POAC peak enhancementAhmed Ayoub, Szabolcs Tõkés. 157-160 [doi]
- Reversible watermarking technique using small-world cellular neural networkKazuya Tsuruta, Yoshifumi Nishio. 157-160 [doi]
- Design of clock generating fully integrated PLL using low frequency reference signalLasse Aaltonen, Mikko Saukoski, Kari Halonen. 161-164 [doi]
- Hybrid lifting scheme using discrete-time cellular neural networks for lossless image codingHisashi Aomori, Tsuyoshi Otake, Nobuaki Takahashi, Mamoru Tanaka. 161-164 [doi]
- Route to chaos in an opto-electronic systemLaurent Larger, Daniele Fournier-Prunaret. 161-164 [doi]
- A cellular neural network based character recognition systemDaniele Casali, Giovanni Costantini, Massimo Carota. 165-168 [doi]
- A non-autonomous IC chaotic oscillator and its application for random bit generationSerdar Özoguz, Salih Ergün. 165-168 [doi]
- Chaos-based high-EMC spread-spectrum clock generatorLuca Antonio De Michele, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti. 165-168 [doi]
- A CNN for biomedical image processingAndrea Anzalone, Federico Bizzarri, Mauro Parodi, Marco Storace. 169-172 [doi]
- Chaotic dynamics and simulation of Japanese vowel soundsMichael Small, Chi Kong Tse, Tohru Ikeguchi. 169-172 [doi]
- EMI performance of spread spectrum clock signals with respect to the IF bandwidth of the EMC standardAndreas Mögel, Jörg Krupar, Wolfgang M. Schwarz. 169-172 [doi]
- The effects of digital implementation on ZePoC codecStefano Santi, Matias Ballardini, Riccardo Rovatti, Gianluca Setti. 173-176 [doi]
- General impedance synthesizer using minimal configuration of switching convertersJoe C. P. Liu, Chi K. Tse, Franki N. K. Poon, M. H. Pong, William Y. M. Lai. 173-176 [doi]
- Accurate, real-time localization of subminiature inductive transponders: tumor localization as an exampleMike Beigel, John McGary. 173-176 [doi]
- Stability analysis of complete two-stage power-factor-correction power suppliesOctavian Dranga, Chi K. Tse, Siu Chung Wong. 177-180 [doi]
- A new transponder architecture for long-range telemetry applicationsFatih Kocer, Michael P. Flynn. 177-180 [doi]
- Simplified workfunction predistorter noise analysisTroels Studsgaard Nielsen, Saska Lindfors, Torben Larsen. 177-180 [doi]
- Analytical approach for analyzing tapered transmission linesBehnam Faraji, Mohammad Hadi Eghlidi, Khashayar Mehrany, Bizhan Rashidian. 181-184 [doi]
- Resistorless KHN biquad using an DDA (difference diffference amplifier) and two CCCIIs (controlled current conveyor)Serhan Yamaçli, Sadri Özcan, Hakan Kuntman. 181-184 [doi]
- Architecture for model-based UHF RFID system design verificationVojtech Derbek, Josef Preishuber-Pfluegl, Christian Steger, Markus Pistauer. 181-184 [doi]
- Low frequency bidirectional communication transponder for security and automotive applicationsYoubok Lee, James Nolan. 185-188 [doi]
- Modeling and analysis of a relaxation oscillatorAntonio Buonomo, Alessandro Lo Schiavo. 185-188 [doi]
- A fully automated flowgraph analysis tool for MatlabMarko Neitola, Timo Rahkonen. 185-188 [doi]
- UICE: a low-power high-speed cryptographic module for RFID and embedded systemsUlrich Kaiser. 189-192 [doi]
- Phase-error reduction technique for quadrature ring oscillatorsKazuya Yoshizaki, Shigetaka Takagi, Nobuo Fujii. 189-192 [doi]
- Hybrid genetic algorithm engine for high-speed floorplanningMasaya Yoshikawa, Hidekazu Terai. 189-192 [doi]
- FL: a formalism for hardware/software codesignK. L. Man. 193-196 [doi]
- Nth-order low-pass filter employing current differencing transconductance amplifiersAli Tugberk Bekri, Fuat Anday. 193-196 [doi]
- The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycleWei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng. 193-196 [doi]
- OTA-C lowpass design using evolutionary algorithmsDasa Ticha, Pravoslav Martínek. 197-200 [doi]
- 1.8-V second-order ΣΔ modulator in 0.18-μm CMOS technologyJuan M. Carrillo, Miguel A. Montecelo, Harald Neubauer, Hans Hauer, J. Francisco Duque-Carrillo. 197-200 [doi]
- A software toolbox for constructing ensembles of heterogenous linear and nonlinear modelsChristian Merkwirth, Jörg D. Wichard, Maciej Ogorzalek. 197-200 [doi]
- Higher order dynamic element matching by shortened tree-structure in delta-sigma modulatorsEsmaeil Najafi Aghdam, Philippe Bénabès. 201-204 [doi]
- Diagnostics of analog systems using rough setsPiotr Bilski, Zbigniew Walczak, Jacek Wojciechowski. 201-204 [doi]
- Second-order OTA-C filters using a single OTAMasood ul-Hasan, Yichuang Sun, Yisheng Zhu. 201-204 [doi]
- m-C filtersJuan Francisco Fernández-Bootello, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez. 205-208 [doi]
- Design of ΣΔ modulators with reduced number of operational amplifiersCristina Della Fiore, Franco Maloberti. 205-208 [doi]
- Multiple fault diagnosis in analogue circuitsMichal Tadeusiewicz, Stanislaw Halgas. 205-208 [doi]
- A 70dB SFDR CMOS transconductorAntonio J. López-Martín, Ramón González Carvajal, Jaime Ramírez-Angulo. 209-212 [doi]
- The collector-base resistance of a BJTN. Terzopoulos, Khaled Hayatleh, Bryan L. Hart, F. J. Lidgey. 209-212 [doi]
- A DCT-domain postprocessor for color bleeding removalFrançois-Xavier Coudoux, Marc Gazalet, Patrick Corlay. 209-212 [doi]
- Practical considerations on doughnut transistors designPaula López, Matthias Oberst, Harald Neubauer, Johann Hauer, Diego Cabello. 213-216 [doi]
- Data partitioning for parallel implementation of real-time video processing systemsMattias O'Nils, Per-Robert Lilljefjäll, Benny Thörnberg. 213-216 [doi]
- Power-balanced asynchronous logicJulian P. Murphy, Alex Yakovlev. 213-216 [doi]
- A flexible architecture for image reconstruction in H.264/AVC decodersAdam Luczak, Pawel Garstecki. 217-220 [doi]
- A mixed-mode conditioning circuit designed for adaptive smart sensingGuillermo Zatorre-Navarro, Nicolás J. Medrano-Marqués, Santiago Celma Pueyo. 217-220 [doi]
- A power dissipation comparison of ALU-architectures for ASIPsVijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska. 217-220 [doi]
- On the bifurcation properties of a class of differentiable mappingsBarry O'Donnell, Paul F. Curran, Orla Feely. 221-224 [doi]
- Maximal sharing of partial terms in MCM under minimal signed digit representationEduardo A. C. da Costa, Paulo F. Flores, José Monteiro. 221-224 [doi]
- Optimized design of ECL gates with a power constraintAlfio Dario Grasso, Gaetano Palumbo. 221-224 [doi]
- Chaotic motion generation with applications to liquid mixingZhong Zhang, Guanrong Chen. 225-228 [doi]
- Interconnect simulation using FDTD method with variable mesh size techniqueHirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai. 225-228 [doi]
- A new multi-mode multifunction filter using CDBAMehmet Sagbas, Muhammet Köksal. 225-228 [doi]
- Modeling using 1-D map of complex behavior in coupled chaotic circuits with intermittencyYoko Uwate, Yoshifumi Nishio. 229-232 [doi]
- A systematic design procedure for high-speed opamp performance optimizationMatteo Perenzoni, Mattia Malfatti, Fabrizio De Nisi, David Stoppa, Andrea Baschirotto. 229-232 [doi]
- Q-parasitics and their influence to the behaviour of nanoscaled CMOS circuitsFrank Felgenhauer, M. Begoin, Wolfgang Mathis. 229-232 [doi]
- Ladder network modeling for closed-form interconnect time delay determinationGiulio Antonini, Giuseppe Ferri. 233-236 [doi]
- Circuit models for small signal performance of nanodevices based on two-state quantum systemsPier Paolo Civalleri, Marco Gilli, Michele Bonnin. 233-236 [doi]
- th-order class of nonlinear mappingsEmer Condon, Paul F. Curran, Ketan Mistry, Orla Feely. 233-236 [doi]
- CMOL: possible hybrid semiconductor/nanodevice circuitsKonstantin K. Likharev. 237-238 [doi]
- Minimising buffer latency through optimum transistor p-to-n ratio scalingConor Buckley, Sverre Lidholm. 237-240 [doi]
- RC-load analysis of the downconversion mixer IIP2Mikko Hotti, Jussi Ryynänen, Kari Halonen. 237-240 [doi]
- Numerical investigation of energy dissipation in Quantum Cellular Automaton circuitsLuca Bonci, Massimo Macucci. 239-242 [doi]
- Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuitsBilly Tomatsopoulos, Andreas Demosthenous. 241-244 [doi]
- A single package transceiver for quad band EGPRS (GSM/GPRS/EDGE) class 12 applicationsMorgan Fitzgibbon, Diarmuid McSwiney, Dermot O'Keeffe, Jyoti Mondal, David Redmond, William Waldie. 241-244 [doi]
- A scheme to enhance the error-correcting capability of encoded quantum informationHan-Wei Wang, I-Ming Tsai, Chih-Neng Chung, Sy-Yen Kuo. 243-246 [doi]
- Low voltage LC-ladder Gm-C low-pass filters with 42-215 MHz tunable rangeAránzazu Otín, Concepción Aldea, Santiago Celma. 245-248 [doi]
- One method for linear phase lowpass IRR filter designAlfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek. 245-248 [doi]
- A method for compensating the D/A converter frequency response distortion in OFDM systemOlli Väänänen, Mikko Kaltiokallio, Jouko Vankka, Kari Halonen. 247-250 [doi]
- Variable-gain up-conversion mixer with current reuse for 5-GHz W-LAN applicationsCalogero D. Presti, Francesco Carrara, Giuseppe Palmisano. 249-252 [doi]
- Implementation of high-speed digit-serial LDI allpass filtersKrister Landernäs, Johnny Holmberg. 249-252 [doi]
- RLS based MIMO channel identification for FEXT compensation in vectored xDSL systemPawel Turcza, Tomasz Twardowski. 251-254 [doi]
- Metamorphic HEMT amplifier for K- and Ka-band applicationsMikko Varonen, Mikko Kärkkäinen, Pekka Kangaslahti, Kari Halonen. 253-256 [doi]
- Exact convergence analysis of adaptive filter algorithms without persistently exciting conditionHideaki Sakai. 253-256 [doi]
- Equalizer design for discrete multitone systems combining response shortening and spectral shapingTomasz Twardowski, Tomasz P. Zielinski, Pawel Turcza. 255-258 [doi]
- Finite impulse response filter banks realized using switched capacitor techniqueRafal Dlugosz, Pawel Pawlowski, Adam Dabrowski. 257-260 [doi]
- Switched-capacitor body-biasing technique for very low voltage CMOS amplifiersPietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti. 257-260 [doi]
- A FSK demodulator comparison for ultra-low power, low data-rate wireless links in ISM bandsEmanuele Lopelli, Johan van der Tang, Arthur H. M. van Roermund. 259-262 [doi]
- Time-domain distortion as criterion for design of IIR Hilbert transformersGoran Molnar, Mladen Vucic. 261-264 [doi]
- 1-V rail-to-rail bulk-driven CMOS OTA with enhanced gain and gain-bandwidth productJuan M. Carrillo, Guido Torelli, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo. 261-264 [doi]
- A general method for designing sparse antenna arraysSanjit K. Mitra, Mikhail K. Tchobanou, Mikhail I. Bryukhanov. 263-266 [doi]
- CMOS interface for differential capacitive transducersGiuseppe Di Cataldo, Salvatore Pennisi. 265-268 [doi]
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- Signal processing in insect hearing organsAlbert Kern, Ruedi Stoop, M. Göpfert, D. A. Smirnov, B. B. Bezrucko. 305-308 [doi]
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- A realization of FIR system for on-line writer recognitionTakenobu Matsuura, Kazuki Izumi. 319-322 [doi]
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- Modelling mismatch effects in CMOS translinear loops and current mode multipliersMirko Gravati, Maurizio Valle. 373-376 [doi]
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- A learning algorithm for improving the classification speed of support vector machinesJun Guo, Norikazu Takahashi, Tetsuo Nishi. 381-384 [doi]
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- Electronically tunable multi-input single-output voltage-mode filterShahram Minaei, Erkan Yüce, Oguzhan Cicekoglu. 401-404 [doi]
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- Accurate modeling and experimental validation of an injection-locked frequency dividerDavid O'Neill, David Bourke, Zhipeng Ye, Michael Peter Kennedy. 409-412 [doi]
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- A micropower differential charge-balancing switched-capacitor front-end for capacitive microaccelerometersMika Kämäräinen, Mikko Saukoski, Kari Halonen. 421-424 [doi]
- A micropower 2 MHz CMOS frequency reference for capacitive sensor applicationsMatti Paavola, Mika Laiho, Mikko Saukoski, Kari Halonen. 425-428 [doi]
- Impact of process parameter variations on the energy dissipation in adiabatic logicJürgen Fischer, Ettore Amirante, Thomas Nirschl, Philip Teichmann, Stephan Henzler, Doris Schmitt-Landsiedel. 429-432 [doi]
- A design automation tool for low-power signal filters for use in sensor interfacesDidier Van Reeth, Georges G. E. Gielen. 433-436 [doi]
- On designing minimax adjustable wideband fractional delay FIR filters using two-rate approachEwa Hermanowicz, Håkan Johansson. 437-440 [doi]
- Design options of the versatile oversampling two-channel SBC-FDFMUX filter bankMohammed N. Abdulazim, Heinz G. Göckler. 441-444 [doi]
- New linearly tapered window and its application to FIR filter designChethan Visweswar, Sanjit K. Mitra. 445-448 [doi]
- A single chip solution for text-to-speech synthesisOzan Aktan, I. Faik Baskaya, Günhan Dündar. 449-452 [doi]
- A low voltage OTA using MOSFET in the triode region and cascode current mirrorHiroki Sato, Akira Hyogo, Keitaro Sekine. 453-456 [doi]
- Power reduction of ASIPs by distributing the workload on several ASIP-instancesVijayakumar Kalyanaraman, Matthias Müller 0002, Sven Simon 0001, Mario Steinert, Holger Gryska. 457-460 [doi]
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