Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero. Circuit design of a dual-versioning L1 data cache for optimistic concurrency. In David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens, editors, Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. pages 325-330, ACM, 2011. [doi]
Abstract is missing.