Table of Contents

• Active management of timing guardband to save energy in POWER7Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter. 1-11 [doi]
• Bundled execution of recurring traces for energy-efficient general purpose processingShantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August. 12-23 [doi]
• Minimalist open-page: a DRAM page-mode scheduling policy for the many-core eraDimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John. 24-35 [doi]
• The NoX routerMitchell Hayenga, Mikko H. Lipasti. 36-46 [doi]
• A systematic methodology to develop resilient cache coherence protocolsKonstantinos Aisopos, Li-Shiuan Peh. 47-58 [doi]
• Dataflow execution of sequential imperative programs on multicore architecturesGagan Gupta, Gurindar S. Sohi. 59-70 [doi]
• Towards the ideal on-chip fabric for 1-to-many and many-to-1 communicationTushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt. 71-82 [doi]
• Packet chaining: efficient single-cycle allocation for on-chip networksGeorge Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally. 83-94 [doi]
• Resilient microring resonator based photonic networksChristopher Nitta, Matthew K. Farrens, Venkatesh Akella. 95-104 [doi]
• FeatherWeight: low-cost optical arbitration with QoS supportYan Pan, John Kim, Gokhan Memik. 105-116 [doi]
• A new case for the TAGE branch predictorAndré Seznec. 117-127 [doi]
• Identifying and predicting timing-critical instructions to boost timing speculationJing Xin, Russ Joseph. 128-139 [doi]
• Idempotent processor architectureMarc de Kruijf, Karthikeyan Sankaralingam. 140-151 [doi]
• Proactive instruction fetchMichael Ferdman, Cansu Kaynak, Babak Falsafi. 152-162 [doi]
• QsCores: trading dark silicon for scalable energy efficiency with quasi-specific coresGanesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson. 163-174 [doi]
• Pack & Cap: adaptive DVFS and thread packing under power capsRyan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda. 175-185 [doi]
• Preventing PCM banks from seizing too much powerAndrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger. 186-195 [doi]
• CRAM: coded registers for amplified multiportingVignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti. 196-205 [doi]
• ATDetector: improving the accuracy of a commercial data race detector by identifying address transferJiaqi Zhang, Weiwei Xiong, Yang Liu, Soyeon Park, Yuanyuan Zhou, Zhiqiang Ma. 206-215 [doi]
• CoreRacer: a practical memory race recorder for multicore x86 TSO processorsGilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu. 216-225 [doi]
• Manager-client pairing: a framework for implementing coherence hierarchiesJesse G. Beu, Michel C. Rosier, Thomas M. Conte. 226-236 [doi]
• TransCom: transforming stream communication for load balance and efficiency in networks-on-chipAhmed H. Abdel-Gawad, Mithuna Thottethodi. 237-247 [doi]
• Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locationsJason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa. 248-259 [doi]
• System-level integrated server architectures for scale-out datacentersSheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi. 260-271 [doi]
• Architectural support for secure virtualization under a vulnerable hypervisorSeongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh. 272-283 [doi]
• Complementing user-level coarse-grain parallelism with implicit speculative parallelismNikolas Ioannou, Marcelo Cintra. 284-295 [doi]
• Hardware transactional memory for GPU architecturesWilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt. 296-307 [doi]
• Improving GPU performance via large warps and two-level warp schedulingVeynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt. 308-317 [doi]
• Pay-As-You-Go: low-overhead hard-error correction for phase change memoriesMoinuddin K. Qureshi. 318-328 [doi]
• Multi retention level STT-RAM cache designs with a dynamic refresh schemeZhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu. 329-338 [doi]
• A resistive TCAM accelerator for data-intensive computingQing Guo, Xiaochen Guo, Yuxin Bai, Engin Ipek. 339-350 [doi]
• A register-file approach for row buffer caches in die-stacked DRAMsGabriel H. Loh. 351-361 [doi]
• Parallel application memory schedulingEiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt. 362-373 [doi]
• Reducing memory interference in multicore systems via application-aware memory channel partitioningSai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda. 374-385 [doi]
• Accelerating microprocessor silicon validation by exposing ISA diversityNikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González. 386-397 [doi]
• Encore: low-cost, fine-grained transient fault recoveryShuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August. 398-409 [doi]
• Formally enhanced runtime verification to ensure NoC functional correctnessRitesh Parikh, Valeria Bertacco. 410-419 [doi]
• Residue cache: a low-energy low-area L2 cache architecture via compression and partial hitsSoontae Kim, Jongmin Lee 0002, Jesung Kim, Seokin Hong. 420-429 [doi]
• SHiP: signature-based hit predictor for high performance cachingCarole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer. 430-441 [doi]
• PACMan: prefetch-aware cache management for high performance cachingCarole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer. 442-453 [doi]
• Efficiently enabling conventional block sizes for very large die-stacked DRAM cachesGabriel H. Loh, Mark D. Hill. 454-464 [doi]
• A compile-time managed multi-level register file hierarchyMark Gebhart, Stephen W. Keckler, William J. Dally. 465-476 [doi]
• SIMD re-convergence at thread frontiersGregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili. 477-488 [doi]
• A data layout optimization framework for NUCA-based multicoresYuanrui Zhang, Wei Ding, Mahmut T. Kandemir, Jun Liu, Ohyoung Jang. 489-500 [doi]