Table of Contents

• A system for asynchronous high-speed chip to chip communicationPer Torstein Røine. 2-10 [doi]
• An Algebraic Semantics for Object-Oriented Behaviour ModelingJan-Willem G. M. Hubbers, Arthur H. M. ter Hofstede. 4-15 [doi]
• Dynamic logic in four-phase micropipelinesStephen B. Furber, Jianwei Liu. 11-16 [doi]
• A Tool for Practical Reasoning about State Machine DesignsAnthony Cant, Katherine A. Eastaughffe, Maris A. Ozols. 16-26 [doi]
• High-performance asynchronous pipeline circuitsKenneth Y. Yun, Peter A. Beerel, Julio Arceo. 17-28 [doi]
• An Industrial-Strength Method For The Construction Of Formally Verified SoftwarePeter A. Lindsay, David Hemer. 27 [doi]
• An efficient algorithm for deriving logic functions of asynchronous circuitsToshiyuki Miyamoto, Sadatoshi Kumagai. 30-35 [doi]
• Complete state encoding based on the theory of regionsJordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Yakovlev. 36-47 [doi]
• Automatic Analysis Of Functional Program StyleGreg Michaelson. 38-46 [doi]
• Software Visualisation in a Generic Development EnvironmentWarwick Allison, David A. Carrington, Tim Jones, Larry Stewart-Zerba, Geoffrey Watson, Jim Welsh. 47-54 [doi]
• General conditions for the decomposition of state holding elementsSteven M. Burns. 48-57 [doi]
• A Layered Operational Model for Describing Inter-tool Communication in Tool Integration FrameworksJennifer G. Harvey, Chris D. Marlin. 55 [doi]
• Fred: an architecture for a self-timed decoupled computerWilliam F. Richardson, Erik Brunvand. 60-68 [doi]
• Do Formal Methods Really Work?Lin Zucconi, Greg Royle, Karl Reed, John Staples. 66 [doi]
• Counterflow pipeline based dynamic instruction schedulingTony Werner, Venkatesh Akella. 69-79 [doi]
• Teaching Object Orientation: Patterns and ReuseNeil A. B. Gray. 72-80 [doi]
• Static scheduling of instructions on micronet-based asynchronous processorsDamal Kandadai Arvind, Vinod E. F. Rebello. 80-91 [doi]
• Towards Analysing a Class of Object Petri NetsSea Ling, Heinz W. Schmidt. 81-92 [doi]
• Classification-Hierarchy Table: A Methodology for Constructing the Classification TreeTsong Yueh Chen, Pak-Lok Poon. 93 [doi]
• Dynamic hazards and speed independent delay modelNozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian. 94-103 [doi]
• Some limitations to speed-independence in asynchronous circuitsMartin E. Bush, Mark B. Josephs. 104-111 [doi]
• Does Object-Orientation Really Work?Brian Henderson-Sellers, Neil A. B. Gray, Christine Mingins, Liping Zhao. 106 [doi]
• On the correctness of the Sproull counterflow pipeline processorPaul G. Lucassen, Jan Tijmen Udding. 112-120 [doi]
• An Application Of Quantitative Techniques To The Question Of What Contributes To A Successful Software Development ProjectKen Mullin, Stuart Hope. 118-130 [doi]
• Single-track handshake signaling with application to micropipelines and handshake circuitsKees van Berkel, Arjan Bink. 122-133 [doi]
• Analysis of Software System Requirements ModelsElizabeth Haywood, Philip W. Dart. 131 [doi]
• Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuitsMasaaki Maezawa, Itaru Kurosawa, Yoshio Kameda, Takashi Nanya. 134-142 [doi]
• Industry-University Partnerships: The Wave of the Future?Nancy R. Mead. 140 [doi]
• Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timingEckhard Grass, Richard C. S. Morling, Izzet Kale. 143-149 [doi]
• A System for Evaluating the Congruence of Software Process ModelsNazim H. Madhavji. 144 [doi]
• An Integrated Database Reengineering Architecture - A Generic ApproachWie Ming Lim, John V. Harrison. 146-154 [doi]
• Using partial orders for trace theoretic verification of asynchronous circuitsTomohiro Yoneda, Takashi Yoshikawa. 152-163 [doi]
• The Hierarchical Dependence Diagram: Improving Design for Reuse in Object-Oriented Software DevelopmentJian Chen. 155-166 [doi]
• Statechart methodology for the design, validation, and synthesis of large scale asynchronous systemsRakefet Kol, Ran Ginosar, Goel Samuel. 164-174 [doi]
• More on the E-measure of Subdomain Testing StrategiesTsong Yueh Chen, Yuen-Tak Yu. 167 [doi]
• Characterizing metastabilityClark Foley. 175-184 [doi]
• Distributing the Software ProcessIgor Hawryszkiewycz, Ian Gorton. 176-182 [doi]
• Consistency Issues in Partially Bound Dynamically Composed SystemsBradley R. Schmerl, Chris D. Marlin. 183-191 [doi]
• The energy and entropy of VLSI computationsJosé A. Tierno, Rajit Manohar, Alain J. Martin. 188-196 [doi]
• An Initial Comparison of Software and Engineering Designs of Automotive Cruise Control SystemsJason Baragry. 192-202 [doi]
• A low-power asynchronous data-path for a FIR filter bankLars Skovby Nielsen, Jens Sparsø. 197-207 [doi]
• Comparing Inspection Strategies for Software Requirement SpecificationsBenjamin Cheng, D. Ross Jeffery. 203 [doi]
• The AMULET2e cache systemJim D. Garside, Steve Temple, R. Mehra. 208-217 [doi]
• Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuitsMarco A. Peña, Jordi Cortadella. 222-232 [doi]
• Control resynthesis for control-dominated asynchronous designsTilman Kolks, Steven Vercauteren, Bill Lin. 233-243 [doi]
• Optimizing average-case delay in technology mapping of burst-mode circuitsPeter A. Beerel, Kenneth Y. Yun, Wei-Chun Chou. 244-260 [doi]