A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter - researchr publication

researchr

You are not signed in
Sign in
Sign up

Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka. A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 10-11, IEEE, 2022. [doi]

Abstract is missing.

runs on WebDSL