A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator

Tsung-Te Liu, Chorng-Kuang Wang. A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator. In Michiel Steyaert, C. L. Claeys, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2004, Leuven, Belgium, September 21-23, 2004. pages 375-378, IEEE, 2004. [doi]

Abstract

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