Gerry C. T. Leung - researchr alias

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Viewing Publication 1 - 5 from 5

2006

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS processAlan W. L. Ng, Gerry C. T. Leung, Ka Chun Kwok, Lincoln Lai Kan Leung, Howard C. Luong. jssc, 41(6):1236-1244, 2006. [doi]

2004

A 1-V 5.2-GHz CMOS synthesizer for WLAN applicationsGerry C. T. Leung, Howard C. Luong. jssc, 39(11):1873-1882, 2004. [doi]

2003

A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delayGerry C. T. Leung, Howard C. Luong. esscirc 2003: 109-112 [doi]

A 1-V 5.2-GHz 27.5-mW fully-integrated CMOS WLAN synthesizerGerry C. T. Leung, Howard C. Luong. esscirc 2003: 113-116 [doi]

2002

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizerToby Kwok-Kei Kan, Gerry C. T. Leung, Howard C. Luong. jssc, 37(8):1012-1020, 2002. [doi]

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