Rong-Jyi Yang - researchr alias

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Viewing Publication 1 - 13 from 13

2016

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWMWei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang. tvlsi, 24(1):17-25, 2016. [doi]

2015

Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay LineChia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang. tvlsi, 23(3):567-574, 2015. [doi]

2012

A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithmWei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen. ispacs 2012: 338-342 [doi]

2008

An All-Digital Fast-Locking Programmable DLL-Based Clock GeneratorChuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu. tcas, 55-I(1):361-369, 2008. [doi]

A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisitionChi-Shuang Oulee, Rong-Jyi Yang. apccas 2008: 680-683 [doi]

2007

A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR AlgorithmRong-Jyi Yang, Shen-Iuan Liu. jssc, 42(2):361-373, 2007. [doi]

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS TechnologyRong-Jyi Yang, Shen-Iuan Liu. jssc, 42(11):2338-2347, 2007. [doi]

2006

A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuitRong-Jyi Yang, Kuan-Hua Chao, Shen-Iuan Liu. tcas, 53(4):842-847, 2006. [doi]

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuitRong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu. jssc, 41(6):1380-1390, 2006. [doi]

2005

A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency DetectorRong-Jyi Yang, Shen-Iuan Liu. ieicet, 88-C(8):1726-1730, 2005. [doi]

A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLsRong-Jyi Yang, Shen-Iuan Liu. ieicet, 88-C(6):1248-1252, 2005. [doi]

2004

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnectionHsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu. tcas, 51-I(12):2356-2364, 2004. [doi]

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 EthernetRong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu. jssc, 39(8):1356-1360, 2004. [doi]

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