Chi-Shuang Oulee, Rong-Jyi Yang. A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition. In IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008. pages 680-683, IEEE, 2008. [doi]
Abstract is missing.