A deep sub-micron timing measurement circuit using a single-stage Vernier delay line - researchr publication

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Antonio H. Chan, Gordon W. Roberts. A deep sub-micron timing measurement circuit using a single-stage Vernier delay line. In Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002. pages 77-80, IEEE, 2002. [doi]

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