Kyu-hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim. An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. J. Solid-State Circuits, 42(1):193-200, 2007. [doi]
Abstract is missing.