Kyu-hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim. An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. J. Solid-State Circuits, 42(1):193-200, 2007. [doi]
@article{KimCKPJKPKCCK07,
title = {An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme},
author = {Kyu-hyoun Kim and Hoeju Chung and Woo-Seop Kim and Moon-Sook Park and Young-Chan Jang and Jinyoung Kim and Hwan-Wook Park and Uksong Kang and Paul W. Coteus and Joo-Sun Choi and Changhyun Kim},
year = {2007},
doi = {10.1109/JSSC.2006.888297},
url = {https://doi.org/10.1109/JSSC.2006.888297},
researchr = {https://researchr.org/publication/KimCKPJKPKCCK07},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {42},
number = {1},
pages = {193-200},
}