An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme - researchr publication authors

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Kyu-hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim. An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. J. Solid-State Circuits, 42(1):193-200, 2007. [doi]

This author has not been identified. Look up 'Kyu-hyoun Kim' in GoogleThis author has not been identified. Look up 'Hoeju Chung' in GoogleThis author has not been identified. Look up 'Woo-Seop Kim' in GoogleThis author has not been identified. Look up 'Moon-Sook Park' in GoogleThis author has not been identified. Look up 'Young-Chan Jang' in GoogleThis author has not been identified. Look up 'Jinyoung Kim' in GoogleThis author has not been identified. Look up 'Hwan-Wook Park' in GoogleThis author has not been identified. Look up 'Uksong Kang' in GoogleThis author has not been identified. Look up 'Paul W. Coteus' in GoogleThis author has not been identified. Look up 'Joo-Sun Choi' in GoogleThis author has not been identified. Look up 'Changhyun Kim' in Google

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