Table of Contents

• Continuous real-world inputs can open up alternative accelerator designsBilel Belhadj, Antoine Joubert, Zheng Li, Rodolphe Héliot, Olivier Temam. 1-12 [doi]
• Flicker: a dynamically adaptive architecture for power limited multicore systemsPaula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker. 13-23 [doi]
• Convolution engine: balancing efficiency & flexibility in specialized computingWajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark A. Horowitz. 24-35 [doi]
• Thin servers with smart pipes: designing SoC accelerators for memcachedKevin T. Lim, David Meisner, Ali G. Saidi, Parthasarathy Ranganathan, Thomas F. Wenisch. 36-47 [doi]
• Understanding and mitigating refresh overheads in high-density DDR4 DRAM systemsJanani Mukundan, Hillery C. Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez. 48-59 [doi]
• An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanismsJamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu. 60-71 [doi]
• ArchShield: architectural framework for assisting DRAM scaling by tolerating high error ratesPrashant Nair, Dae-Hyun Kim, Moinuddin K. Qureshi. 72-83 [doi]
• Improving memory scheduling via processor-side load criticality informationSaugata Ghose, Hyodong Lee, José F. Martínez. 84-95 [doi]
• Agile, efficient virtualization power management with low-latency server power statesCanturk Isci, Suzanne McIntosh, Jeffrey O. Kephart, Rajarshi Das, James E. Hanson, Scott Piper, Robert R. Wolford, Thomas Brey, Robert Kantner, Allen Ng, James Norris, Abdoulaye Traore, Michael Frissora. 96-107 [doi]
• Secure I/O device sharing among virtual machines on multiple hostsCheng-Chun Tu, Chao-tang Lee, Tzi-cker Chiueh. 108-119 [doi]
• Improving virtualization in the presence of software managed translation lookaside buffersXiaotao Chang, Hubertus Franke, Yi Ge, Tao Liu, Kun Wang, Jimi Xenidis, Fei Chen, Yu Zhang. 120-129 [doi]
• Microarchitectural mechanisms to exploit value structure in SIMT architecturesJi Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten. 130-141 [doi]
• Triggered instructions: a control paradigm for spatially-programmed architecturesAngshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer. 142-153 [doi]
• Utility-based acceleration of multithreaded applications on asymmetric CMPsJosé A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt. 154-165 [doi]
• Quantum rotations: a case study in static and dynamic machine-code generation for quantum computersDaniel Kudrow, Kenneth Bier, Zhaoxia Deng, Diana Franklin, Yu Tomita, Kenneth R. Brown, Frederic T. Chong. 166-176 [doi]
• DNA-based molecular architecture with spatially localized componentsRichard A. Muscat, Karin Strauss, Luis Ceze, Georg Seelig. 177-188 [doi]
• AC-DIMM: associative computing with STT-MRAMQing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek, Eby G. Friedman. 189-200 [doi]
• Exploring memory consistency for massively-threaded throughput-oriented processorsBlake A. Hechtman, Daniel J. Sorin. 201-212 [doi]
• WeeFence: toward making fences free in TSOYuelu Duan, Abdullah Muzahid, Josep Torrellas. 213-224 [doi]
• Robust architectural support for transactional memory in the power architectureHarold W. Cain, Maged M. Michael, Brad Frey, Cathy May, Derek Williams, Hung Le. 225-236 [doi]
• Efficient virtual memory for big memory serversArkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark D. Hill, Michael M. Swift. 237-248 [doi]
• Navigating big data with high-throughput, energy-efficient data partitioningLisa Wu, Raymond J. Barker, Martha A. Kim, Kenneth A. Ross. 249-260 [doi]
• LINQits: big data on little clientsEric S. Chung, John D. Davis, Jaewon Lee. 261-272 [doi]
• STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction executionIslam Atta, Pinar Tözün, Xin Tong, Anastasia Ailamaki, Andreas Moshovos. 273-284 [doi]
• Cooperative boosting: needy versus greedy power managementIndrani Paul, Srilatha Manne, Manish Arora, William Lloyd Bircher, Sudhakar Yalamanchili. 285-296 [doi]
• Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processorsAnys Bacha, Radu Teodorescu. 297-307 [doi]
• A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsivenessHenry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David A. Patterson, Krste Asanovic. 308-319 [doi]
• Catnap: energy proportional multiple network-on-chipReetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski. 320-331 [doi]
• Orchestrated scheduling and prefetching for GPGPUsAdwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, Chita R. Das. 332-343 [doi]
• An energy-efficient and scalable eDRAM-based register file architecture for GPGPUNaifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang. 344-355 [doi]
• Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutationMinsoo Rhu, Mattan Erez. 356-367 [doi]
• SIMD divergence optimization through intra-warp compactionAniruddha S. Vaidya, Anahita Shayesteh, Dong Hyuk Woo, Roy Saharoy, Mani Azimi. 368-379 [doi]
• Reducing memory access latency with asymmetric DRAM bank organizationsYoung Hoon Son, O. Seongil, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn. 380-391 [doi]
• CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAMZiyi Liu, Jong Hyuk Lee, Junyuan Zeng, Yuanfeng Wen, Zhiqiang Lin, Weidong Shi. 392-403 [doi]
• Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cacheDjordje Jevdjic, Stavros Volos, Babak Falsafi. 404-415 [doi]
• Resilient die-stacked DRAM cachesJaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor. 416-427 [doi]
• Bit mapping for balanced PCM cell programmingYu Du, Miao Zhou, Bruce R. Childers, Daniel Mossé, Rami G. Melhem. 428-439 [doi]
• Tri-level-cell phase change memory: toward an efficient and reliable memory systemNak Hee Seong, Sungkap Yeo, Hsien-Hsin S. Lee. 440-451 [doi]
• Zombie memory: extending memory lifetime by reviving dead blocksRodolfo Azevedo, John D. Davis, Karin Strauss, Parikshit Gopalan, Mark Manasse, Sergey Yekhanin. 452-463 [doi]
• QuickSAN: a storage area network for fast, distributed, solid state disksAdrian M. Caulfield, Steven Swanson. 464-474 [doi]
• ZSim: fast and accurate microarchitectural simulation of thousand-core systemsDaniel Sanchez, Christos Kozyrakis. 475-486 [doi]
• GPUWattch: enabling energy optimizations in GPGPUsJingwen Leng, Tayler H. Hetherington, Ahmed ElTantawy, Syed Zohaib Gilani, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi. 487-498 [doi]
• Studying multicore processor scaling via reuse distance analysisMeng-Ju Wu, Minshu Zhao, Donald Yeung. 499-510 [doi]
• Criticality stacks: identifying critical threads in parallel programs using synchronization behaviorKristof Du Bois, Stijn Eyerman, Jennifer B. Sartor, Lieven Eeckhout. 511-522 [doi]
• The locality-aware adaptive cache coherence protocolGeorge Kurian, Omer Khan, Srinivas Devadas. 523-534 [doi]
• A new perspective for efficient virtual-cache coherenceStefanos Kaxiras, Alberto Ros. 535-546 [doi]
• Protozoa: adaptive granularity cache coherenceHongzhou Zhao, Arrvindh Shriraman, Snehasish Kumar, Sandhya Dwarkadas. 547-558 [doi]
• On the feasibility of online malware detection with performance countersJohn Demme, Matthew Maycock, Jared Schmitz, Adrian Tang, Adam Waksman, Simha Sethumadhavan, Salvatore J. Stolfo. 559-570 [doi]
• Design space exploration and optimization of path oblivious RAM in secure processorsLing Ren, Xiangyao Yu, Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas. 571-582 [doi]
• SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chipHassan M. G. Wassel, Ying Gao, Jason Oberg, Ted Huffmire, Ryan Kastner, Frederic T. Chong, Timothy Sherwood. 583-594 [doi]
• Virtualizing power distribution in datacentersDi Wang, Chuangang Ren, Anand Sivasubramaniam. 595-606 [doi]
• Bubble-flux: precise online QoS management for increased utilization in warehouse scale computersHailong Yang, Alex Breslow, Jason Mars, Lingjia Tang. 607-618 [doi]
• Whare-map: heterogeneity in "homogeneous" warehouse-scale computersJason Mars, Lingjia Tang. 619-630 [doi]
• Deconfigurable microprocessor architectures for silicon debug accelerationNikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González. 631-642 [doi]
• QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programsGilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Emile Gottschlich, Nima Honarmand, Nathan Dautenhahn, Samuel T. King, Josep Torrellas. 643-654 [doi]
• Non-race concurrency bug detection through order-sensitive critical sectionsRuirui C. Huang, Erik Halberg, G. Edward Suh. 655-666 [doi]