Multi Strobe Circuit for 2.133GHz Memory Test System

Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka. Multi Strobe Circuit for 2.133GHz Memory Test System. In Scott Davidson, Anne Gattiker, editors, 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006. pages 1-9, IEEE, 2006. [doi]

Abstract

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