Abstract is missing.
- Minimizing channel density with movable terminalsRonald I. Greenberg, Jau-Der Shih. 1-5 [doi]
- VICTOR: A three-layer over-the-cell routerTimothy W. Strunk, Nancy D. Holmes. 6-10 [doi]
- Modeling the vertical constraints in VLSI channel routingAntonije D. Jovanovic. 11-13 [doi]
- Modeling stuck-open faults in CMOS iterative circuitsEnrico Macii, Qing Xu. 14-17 [doi]
- Delay fault testability evaluation through timing simulationSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal. 18-21 [doi]
- C-testable systolic arraysNikrouz Faroughi. 22-26 [doi]
- A VLSI-based digital multilayer neural network architectureYoung-Chul Kim 0001, Michael A. Shanblatt. 27-31 [doi]
- Neural system design with the integrated neurocomputing architecturePaul Mukai, Mark Busa, Peter T. Kazlas. 32-36 [doi]
- A parallel VLSI implementation of Viterbi algorithm for accelerated word recognitionV. Upadhyaya, Shambhu Upadhyaya, A. Kundu. 37-41 [doi]
- Clock partitioning for testabilityKent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal. 42-46 [doi]
- Locally clocked microprocessorStephen J. Muscato, Alexander Albicki. 47-51 [doi]
- A simple method for noise tolerance characterization of digital circuitsSlobodan Simovich, Paul D. Franzon, Michael B. Steer. 52-56 [doi]
- Switchbox routing with movable terminalsJon Hamkins, Donna J. Brown. 57-61 [doi]
- Mixed spanning trees: a technique for performance-driven routingJeffrey S. Salowe, Dana S. Richards, Dallas E. Wrege. 62-66 [doi]
- Corner stitching for L-shaped tilesGeorge Blust, Dinesh P. Mehta. 67-68 [doi]
- Parallel genetic algorithm for channel routingB. B. Prahlada Rao, Lalit M. Patnaik, R. C. Hansdah. 69-70 [doi]
- Optimal register allocation in high level synthesisS. Aranake, Vijay K. Raj, M. Vashi, Hee Yong Youn. 71-75 [doi]
- Efficient minimization algorithms for fixed polarity AND/XOR canonical networksChien-Chung Tsai, Malgorzata Marek-Sadowska. 76-79 [doi]
- Rate-optimal static scheduling for DSP data-flow programsLiang-Fang Chao, Edwin Hsing-Mean Sha. 80-84 [doi]
- Rapid-prototyping of high-assurance systemsRichard Auletta, Cherrice Traver. 85-89 [doi]
- Toward a Steiner engine: enhanced serial and parallel implementations of the iterated 1-Steiner MRST algorithmTim Barrera, Jeff Griffith, Sally A. McKee, Gabriel Robins, Tongtong Zhang. 90-94 [doi]
- A potential-driven approach to constructing rectilinear Steiner treesS. C. Gadre, Ramachandran Vaidyanathan, Si-Qing Zheng. 95-99 [doi]
- Minmax-cut graph partitioning problemsSpyros Tragoudas. 100-104 [doi]
- Local improvement in Steiner treesForbes D. Lewis, Wang Chia-Chi Pong, Nancy K. Van Cleave. 105-106 [doi]
- Δ-trees of a graph: introduction and formal definitionJason K. Davis, Enrico Macii. 107-108 [doi]
- Automating the packaging selection of VLSI systemsGary W. Panzer. 109-113 [doi]
- Adaptive bounded time windows in an optimistically synchronized simulatorAvinash C. Palaniswamy, Philip A. Wilsey. 114-118 [doi]
- Optimizing carry lookahead adders for semicustom CMOSClark D. Thomborson, Yi Sun. 119-122 [doi]
- A logic synthesis system based on global dynamic extraction and flexible costYulin Chen, Wei Kang Tsai, Fadi J. Kurdahi. 123-126 [doi]
- VLSI synthesis of a programmable DWT chip for the optimal choice of a prototype waveletSubra Ganesan, S. Mahalingam, S. Nagabhushana. 127-131 [doi]
- MinMux: a new approach for global minimization of multiplexers in interconnect synthesisThomas Charles Wilson, M. K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji. 132-138 [doi]
- A new state assignment technique for asynchronous finite state machinesTam Anh Chu, Narayana Mani, Clement K. C. Leung. 139-143 [doi]