V. Upadhyaya, Shambhu Upadhyaya, A. Kundu. A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition. In Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993. pages 37-41, IEEE, 1993. [doi]
Abstract is missing.