V. Upadhyaya, Shambhu Upadhyaya, A. Kundu. A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition. In Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993. pages 37-41, IEEE, 1993. [doi]
@inproceedings{UpadhyayaUK93,
title = {A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition},
author = {V. Upadhyaya and Shambhu Upadhyaya and A. Kundu},
year = {1993},
doi = {10.1109/GLSV.1993.224485},
url = {http://dx.doi.org/10.1109/GLSV.1993.224485},
researchr = {https://researchr.org/publication/UpadhyayaUK93},
cites = {0},
citedby = {0},
pages = {37-41},
booktitle = {Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993},
publisher = {IEEE},
isbn = {0-8186-3430-8},
}