Abstract is missing.
- Physical Design for 3D Chiplets and System IntegrationFrank J. C. Lee. 1 [doi]
- Reinforcement Learning for Electronic Design Automation: Successes and OpportunitiesMatthew E. Taylor. 3 [doi]
- Reinforcement Learning for Placement OptimizationAnna Goldie, Azalia Mirhoseini. 5 [doi]
- The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural NetworksYi-Chen Lu, Sai Pentapati, Sung Kyu Lim. 7-14 [doi]
- Advancing PlacementAndrew B. Kahng. 15-22 [doi]
- A Fast Optimal Double Row Legalization AlgorithmStefan Hougardy, Meike Neuwohner, Ulrike Schorr. 23-30 [doi]
- Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height DesignsBo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang. 31-38 [doi]
- Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICsPruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, Sung Kyu Lim. 39-46 [doi]
- Still Benchmarking After All These YearsIsmail S. Bustany, Jinwook Jung, Patrick H. Madden, Natarajan Viswanathan, Stephen Yang. 47-52 [doi]
- Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore EraIvo Bolsens. 53-54 [doi]
- Learning Point Clouds in EDAWei Li, Guojin Chen, Haoyu Yang, Ran Chen, Bei Yu 0001. 55-62 [doi]
- Building up End-to-end Mask Optimization Framework with Self-trainingBentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young. 63-70 [doi]
- Machine Learning Techniques in Analog Layout AutomationTonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. 71-72 [doi]
- Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V MicroprocessorGage Hills. 73 [doi]
- ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip OptimizationSai Surya Kiran Pentapati, Bon Woong Ku, Sung Kyu Lim. 75-82 [doi]
- Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process NodesSiddhartha Nath, Vishal Khandelwal. 83-90 [doi]
- A Fast Power Network Optimization Algorithm for Improving Dynamic IR-dropJai-Ming Lin, Yang-Tai Kung, Zheng-Yu Huang, I-Ru Chen. 91-98 [doi]
- A Lifetime of ICs, and Cross-field Exploration: ISPD 2021 Lifetime Achievement Award BioLouis K. Scheffer. 99-100 [doi]
- The Physical Design of Biological Systems - Insights from the Fly BrainLouis K. Scheffer. 101-108 [doi]
- Of Brains and ComputersJan M. Rabaey. 109 [doi]
- EDA and Quantum Computing: The key role of Quantum CircuitsLeon Stok. 111 [doi]
- Physical Verification at Advanced Technology Nodes and the Road AheadJuan C. Rey. 113 [doi]
- Hardware Security for and beyond CMOS TechnologyJohann Knechtel. 115-126 [doi]
- Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration TechnologiesLingjun Zhu, Sung Kyu Lim. 127-134 [doi]
- A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAsGanesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon. 135-142 [doi]
- ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and RoutingPatrick Groeneveld, Michael James 0002, Vladimir Kibardin, Ilya Sharapov, Marvin Tom, Leo Wang. 143-147 [doi]