Table of Contents

• Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design MethodologyAnagha Nimbekar, Prabodh Katti, Chen Li, Bashir M. Al-Hashimi, Amit Acharyya, Bipin Rajendran. 1-6 [doi]
• Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6GChristian Maximilian Karle, Marc Neu, Benjamin Nuss, Lukas Witte, Andre Scheder, Eva Waldner, Ema Shkurtaj, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• Quantum Implementation of Linear and Non-Linear LayersAnubhab Baksi, Sumanta Chakraborty, Anupam Chattopadhyay, Matthew Chun, SK Hafizul Islam, Kyungbae Jang, HyunJi Kim, Yujin Oh, Soham Roy, Hwajeong Seo, Siyi Wang. 1-6 [doi]
• Hardware Design Space Exploration in High-Level Synthesis Backend Featuring Online ArithmeticSaeid Gorgin 0001, Mohammad K. Fallah, Mohammad Sina Karvandi, Jeong-A Lee. 1-6 [doi]
• User-Authenticated Device-Independent Quantum Secure Direct Communication ProtocolNayana Das, Saikat Basu, Goutam Paul 0001, Vijay S. Rao. 1-6 [doi]
• Performance Investigation for IEEE 802.15.4z-compliant SiP-assisted RangingJanik Kaden, Erik Markert, Ulrich Heinkel. 1-6 [doi]
• Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoCAhmed Kamaleldin, Matthias Nickel, Sisi Wu, Diana Göhringer. 1-6 [doi]
• DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest Path and Coverage AreaInfall Syafalni, Mohamad Imam Firdaus, Nana Sutisna, Trio Adiono, Tutun Juhana, Rahmat Mulyawan. 1-6 [doi]
• A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event InterpretationMarc Neu, Christian Maximilian Karle, Patrick Schmidt, Julian Höfer, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• RVVe: A Minimal RISC-V Vector Processor for Embedded AI AccelerationPatrick Schmidt, Johannes Pfau, Tim Hotfilter, Matthias Stammler, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• Lockstep Vs Microarchitecture: A ComparisonJán Mach, Lukás Kohútka, Pavel Cicák. 1-6 [doi]
• Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based MethodWuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang. 1-6 [doi]
• ZeKi: A Zero-Knowledge Dynamic Logic Locking Implementation with Resilience to Multiple AttacksYue Zhang, Basel Halak, Haoyu Wang. 1-6 [doi]
• MCLB: Dynamic Load Balancing and Implications on GPU Memory ControllersVahid Geraeinejad, Kun-Chih Jimmy Chen, Zhonghai Lu, Masoumeh Ebrahimi. 1-6 [doi]
• On Metric-Driven Development of Embedded Neuromorphic AIJann Krausse, Moritz Neher, Iris Fürst-Walter, Carmen Weigelt, Tanja Harbaum, Klaus Knobloch, Jürgen Becker 0001. 1-6 [doi]
• 16-Bit SABP: Quasi-Stochastic Data Representation Unit for AI Hardware Using FPGAMarwan A. Abdelfattah, Hossam O. Ahmed, Mohamed A. Abdelghany. 1-6 [doi]
• Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based SystemsShuang Liu, Martin Radetzki. 1-6 [doi]
• Usage Driven Relevance Analysis for IP CoresLutz Schammer, Gianluca Martino, Görschwin Fey. 1-6 [doi]
• Hardware-Aware Network Adaptation using Width and Depth Shrinking including Convolutional and Fully Connected Layer MergingPratibha Verma, Tarun Gupta, Pabitra Das, Appa Rao Nali, Vidhumouli Hunsigida, Amit Acharyya. 1-6 [doi]
• A Systematic Study of Parallelization Strategies for Optimizing Scientific Computing Performance BoundsVijayalakshmi Saravanan, Sai Karthik Navuluru, Khaled Z. Ibrahim. 1-6 [doi]
• KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting TransformerAness Al-Qawlaq, M. Ajay Kumar, Deepu John. 1-6 [doi]
• COSSEA: Context-based SoC Security Enforcement ArchitectureCarsten Heinz, Andreas Koch 0001. 1-6 [doi]
• Exploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the EdgeLiu He, Yujin Wang, Zongle Huang, Shupei Fan, Chen Tang, Shuyuan Zhang, Luchang Lei, Huazhong Yang, Yongpan Liu, Hongyang Jia. 1-6 [doi]
• Mitigation of Hardware Trojan in NoC using Delta-Based CompressionHamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau. 1-6 [doi]
• Digital Twin Based Run Time Power Management for Edge SoC using Performance Aware Reinforcement LearningRatnala Vinay, Kartik Laad, Parveen Nisha, Afreen Aijaz, Bhavya Pisipati, Pradip Sasmal, Toshihisa Haraki, Chirag Juyal, Yuki Tanimoto, Amit Acharyya. 1-6 [doi]
• Efficient Deployment of Large Language Model across Cloud-Device SystemsFan Yang, Zehao Wang, Haoyu Zhang, Zhenhua Zhu, Xinhao Yang, Guohao Dai, Yu Wang 0002. 1-6 [doi]
• Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced ReliabilityYu-Guang Chen, Yi-Chen Ho, Jing-Yang Jou. 1-6 [doi]
• Ultra-NoC: Unified Low-Transmission Routing Assisted NoC for High-flexible DNN AcceleratorKun-Chih Jimmy Chen, Hao-Hsiang Peng, Pin-Ching Shen. 1-5 [doi]
• BEACON: Block-wise Efficient Architecture Co-optimization for DNN-HW-Mapping with Zero-cost Evaluation and Progressive DistillationJiun-Kai Yang, Yao-Hua Chen, Chih-Tsun Huang. 1-6 [doi]
• Accurate Charge-Domain Bootstrapped Computing-in-Memory SRAM Design with Wide Programmable Output Voltage RangeFuyi Li, Yu Xia, Shuai Xiao, Pengcheng Yang, Xingyu Zhu, Bo Li, Jiuren Zhou, Genquan Han, Wei Mao 0002. 1-6 [doi]
• GELU-MSDF: A Hardware Accelerator for Transformer's GELU Activation Function Using Most Significant Digit First ComputationAlireza Taghavizade, Dara Rahmati, Saeid Gorgin 0001, Jeong-A Lee. 1-6 [doi]
• Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G DevelopmentChristian Maximilian Karle, Marc Neu, Benjamin Nuss, Jiayi Chen, Lukas Witte, Andre Scheder, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS ChipToshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura. 1-6 [doi]
• Energy-Efficient and Communication-Aware Architectures for Accelerating Deep Learning WorkloadsA. Alper Goksoy, Jiahao Lin, Ümit Y. Ogras. 1-6 [doi]
• An Automated Hardware Design Framework for Various DNNs Based on ChatGPTQiuhao Zeng, Yuefei Wang, Zhongfeng Wang 0001, Wendong Mao. 1-6 [doi]
• DeepShield: Lightweight Privacy-Preserving Inference for Real-Time IoT Botnet DetectionSabbir Ahmed Khan, Zhuoran Li, Woosub Jung, Yizhou Feng, Dan Zhao, Chunsheng Xin, Gang Zhou. 1-6 [doi]
• Analog Circuits Fault Diagnosis Based on Machine LearningHuapei Wang, Cheng Cai, Xuxin Chen, Fang Huo. 1-6 [doi]
• Robust Learning-to-Rank Algorithm for Bug Discovery in Hardware VerificationHongsup Shin. 1-2 [doi]
• Evaluating Deep Neural Network Performance on Edge Accelerators: A Roofline Model Adopted Benchmarking ApproachPrashanth H. C., Madhav Rao. 1-6 [doi]
• Accelerating Automated Driving and ADAS Using HW/SW CodesignShubham Rai, Cecilia De la Parra, Martin Rapp, Jan Micha Borrmann, Nina Bretz, Stefan Metzlaff, Taha Soliman, Christoph Schorn. 1-6 [doi]
• Clustering-Based-Approach for Hardware Implementation of Activation FunctionsMahati Basavaraju, Omkar Girish Ratnaparkhi, Vinay Rayapati, Madhav Rao. 1-6 [doi]
• Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP CoresAgshare Dheeraj, Pabitra Das, Yv Sai Dinesh, Anagha Nimbekar, Amit Acharyya. 1-6 [doi]
• Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSIShintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe. 1-6 [doi]
• EdgeVision SoC: PPA-Impact of RTL-level ModificationsMikail Yayla, Clifford Leon Dmello, Georg Ellguth, Uwe Steeb, Tim Leuchter, Marcus Pietzsch, Holger Eisenreich. 1-2 [doi]
• Pressure-Activated RF Sensing: A Smart Cushion Approach for Energy-Efficient IoT Health MonitoringImran M. Saied, Anil Kumar Appukuttan Nair Syamala Amma, Srinjoy Mitra, Tughrul Arslan. 1-6 [doi]
• Fully Integrated Switched-Capacitor DC-DC Converter With Self-Recovery Hysteresis ControlKoji Kikuta, Takashi Hisakado, Mahfuzul Islam. 1-6 [doi]
• EDEA: Efficient Dual-Engine Accelerator for Depthwise Separable Convolution with Direct Data TransferYi Chen, Jie Lou, Malte Wabnitz, Johnson Loh, Tobias Gemmeke. 1-6 [doi]
• Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical DesignYeongyeong Shin, Taewhan Kim. 1-6 [doi]
• Heloc-NoC: High-Efficiency and Low-Hop On-Chip Communication in 3D Network-on-ChipsLizhong Wang, Haoyu Wang. 1-6 [doi]
• Exploring the Potential of Dynamic Quantum Circuit for Improving Device ScalabilityAbhoy Kole, Kamalika Datta, Rolf Drechsler. 1-5 [doi]
• A Low-voltage-Driven Single-ended Column based SRAM for Low-Power Micro-displayShubham Ranjan, Sheida Gohardehi, Manoj Sachdev. 1-6 [doi]
• Beyond Total Locking: Demonstrating and Measuring Mutual Influence on a RO-Based True Random Number Generator on an FPGAEloïse Delolme, Viktor Fischer, Florent Bernard, Nathalie Bochard, Maxime Pelcat. 1-6 [doi]
• PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip ArchitecturesDipal Halder, Yuntao Liu, Kostas Amberiadis, Ankur Srivastava, Sandip Ray. 1-6 [doi]
• Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware AcceleratorsRobin Geens, Man Shi, Arne Symons, Chao Fang, Marian Verhelst. 1-6 [doi]
• Generative AI Augmented Induction-based Formal VerificationAman Kumar, Deepak Narayan Gadde. 1-2 [doi]
• Improving Timing Quality Through Net Topology Optimization in Global RoutingJayoung Yang, Taewhan Kim. 1-6 [doi]
• Evaluating the Performance of Large Language Models for Design ValidationAbdur Rahman, Goerschwin Fey. 1-6 [doi]
• GATrojan: An Efficient Gate-level Hardware Trojan Detection Approach Using Graph Attention NetworksSen Wang, Yijun Cui, Shichao Yu, Chongyan Gu, Chenghua Wang, Weiqiang Liu 0001. 1-6 [doi]
• On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device TechnologiesSiva Satyendra Sahoo, Dawit Burusie Abdi, Julien Ryckaert, James Myers, Dwaipayan Biswas. 1-6 [doi]
• A 8Gb/s PAM-4/NRZ Dual-Mode Transmitter for Panel Interfaces with Run-length Limited Maximum TransitionGoeun Kim, Younghwan Chang, Yong-Un Jeong, Suhwan Kim. 1-5 [doi]
• Hardened-TC: A Low-cost Reliability Solution for CNNs Run by Modern GPUsEhsan Atoofian. 1-6 [doi]
• LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware AcceleratorFabian Kreß, Alexey Serdyuk, Denis Kobsar, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker 0001. 126-131 [doi]
• Assessing the Circuit Requirements for a Real-Time Spectrum Analyzer on 65-nm CMOS TechnologyMojgan Mirzaei Hotkani, Jean-François Bousquet, Bruce Martin, Ehsan Malekshahi. 132-137 [doi]
• Continuous Conduction Mode in Digital Control Loop of DC-DCVenkatesh G. Kadlimatti, Aniruddha Periyapatna Nagendra, M. Ankitha, Harikrishna Parthasarathy. 138-142 [doi]
• HLS based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital SignatureVishal Chourasia, Anirban Sengupta, Rahul Chaurasia. 143-148 [doi]