Table of Contents

• Evaluating the Hardware Performance Counters of an Xtensa Virtual PrototypeAdebayo Omotosho, Sirine IIahi, Ernesto Cristopher Villegas Castillo, Christian Hammer 0001, Christian Sauer 0001. 1-6 [doi]
• Optimizing Packet Classification on FPGAMichal Kekely, Jan Korenek. 7-12 [doi]
• Active Wire Fences for Multitenant FPGAsOgnjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic. 13-20 [doi]
• Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faultsPaolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Vincenzo Tancorre. 21-26 [doi]
• Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree ModelsSwantje Plambeck, Görschwin Fey. 27-32 [doi]
• Reducing Output Response Aliasing Using Boolean Optimization TechniquesRobert Hülle, Petr Fiser, Jan Schmidt. 33-38 [doi]
• Split-Et-Impera: A Framework for the Design of Distributed Deep Learning ApplicationsLuigi Capogrosso, Federico Cunico, Michele Lora, Marco Cristani, Franco Fummi, Davide Quaglia. 39-44 [doi]
• Prediction of Inference Energy on CNN Accelerators Supporting Approximate CircuitsMichal Pinos, Vojtech Mrazek, Lukás Sekanina. 45-50 [doi]
• NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory ArchitecturesAli Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Masoud Daneshtalab. 51-56 [doi]
• Hardware Acceleration of FHEWJonas Bertels, Michiel Van Beirendonck, Furkan Turan, Ingrid Verbauwhede. 57-60 [doi]
• Supporting analog design for reliability by efficient provision of reliability information to designersFabio A. Velarde Gonzalez, Lukas Hahne, Katrin Ortstein, André Lange, Sonja Crocoll. 61-64 [doi]
• Characterization of Interconnect Fault Effects in SRAM-based FPGAsChristian Fibich, Martin Horauer, Roman Obermaisser. 65-68 [doi]
• LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory ComputingKhakim Akhunov, Kasim Sinan Yildirim. 69-72 [doi]
• Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate NodesRune Krauss, Mehran Goli, Rolf Drechsler. 73-78 [doi]
• High-Throughput Approximate Multiplication Models in PyTorchElias Trommer, Bernd Waschneck, Akash Kumar 0001. 79-82 [doi]
• A Low-cost Residue-based Scheme for Error-resiliency of RNN AcceleratorsNooshin Nosrati, Zainalabedin Navabi. 83-86 [doi]
• HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram PackageLuigi Capogrosso, Luca Geretti, Marco Cristani, Franco Fummi, Tiziano Villa. 87-90 [doi]
• Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial)Vojtech Mrazek. 91-92 [doi]
• Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-VariationsCarl Riehm, Christoph Frisch, Florin Burcea, Matthias Hiller, Michael Pehl, Ralf Brederlow. 93-98 [doi]
• Counterfeit Chip Detection using Scattering Parameter AnalysisMaryam Saadat-Safa, Tahoura Mosavirik, Shahin Tajik. 99-104 [doi]
• Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization TechniquesMarcel Merten, Muhammad Hassan 0002, Rolf Drechsler. 105-110 [doi]
• A Digital Delay Model Supporting Large Adversarial Delay VariationsDaniel Öhlinger, Ulrich Schmid 0001. 111-117 [doi]
• A Lightweight Intrusion Detection System against IoT Memory Corruption AttacksMohamed El Bouazzati, Russell Tessier, Philippe A. Tanguy, Guy Gogniat. 118-123 [doi]
• APPRAISER: DNN Fault Resilience Analysis Employing Approximation ErrorsMahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik. 124-127 [doi]
• A Configurable Mixed-Precision Convolution Processing Unit Generator in ChiselJure Vreca, Anton Biasizzo. 128-131 [doi]
• Open Automation Framework for Complex Parametric Electrical SimulationsSergio Vinagrero Gutierrez, Pietro Inglese, Giorgio Di Natale, Elena Ioana Vatajelu. 132-135 [doi]
• A Low-Cost Combinational Approximate MultiplierZahra Hojati, Zainalabedin Navabi. 136-139 [doi]
• Bits, Flips and RISCsNicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen 0001, Markus Ulbricht 0002, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker. 140-149 [doi]
• Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug CandidatesDominic Korner, Andreas Kramer, Klaus Hofmann, Felix Hausch. 150-154 [doi]
• MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia ClassifiersMartin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina. 155-160 [doi]
• Verifying Bio-Electronic SystemsJoseline Heuer, Rene Krenz-Baath, Roman Obermaisser. 161-166 [doi]
• Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?Letícia Maria Veiras Bolzani. 167-168 [doi]
• A Reliability-aware Environment for Design Exploration for GPU DevicesRobert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 169-174 [doi]
• A Comprehensive Analysis of Transient Errors on Systolic ArraysEleonora Vacca, Sarah Azimi, Luca Sterpone. 175-180 [doi]
• Resilience-Performance Tradeoff Analysis of a Deep Neural Network AcceleratorSalvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez 0001, Alberto Bosio. 181-186 [doi]