Table of Contents

• Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-MemoryShima Hosseinzadeh, Suzanne Lancaster, Amirhossein Parvaresh, Cláudia Silva, Dietmar Fey. 1-10 [doi]
• Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level RepresentationSubrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das. 11-18 [doi]
• Hardware Acceleration of Capsule Networks for Real-Time ApplicationsMaryam Hemmati, Earlene Starling Babette, Julia Shan, Morteza Biglari-Abhari, Smaïl Niar. 19-25 [doi]
• Counter Power Leakage for Frequency Extraction of Ring Oscillators in ROPUFOndrej Stanícek, Filip Kodýtek, Róbert Lórencz. 26-32 [doi]
• Investigation of Commercial Off-The-Shelf ReRAM Modules for Use as Runtime-Accessible TRNGTolga Arul, Nico Mexis, Aleena Elsa George, Florian Frank 0004, Nikolaos Athanasios Anagnostopoulos, Stefan Katzenbeisser 0001. 33-42 [doi]
• Exploring Fault Injection Attacks on CVA6 PMP Configuration FlowKévin Quénéhervé, William Pensec, Philippe Tanguy, Rachid Dafali, Vianney Lapôtre. 43-50 [doi]
• Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash AlgorithmMatús Oleksák, Vojtech Miskovský. 51-56 [doi]
• SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited CutwidthLuca Müller, Rolf Drechsler. 57-64 [doi]
• Studying the Degradation of Propagation Delay on FPGAs at the European XFELLeandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt. 65-72 [doi]
• Influence of Structural Units on Vulnerability of Systems with Distinct Protection ApproachesJán Mach, Lukás Kohútka, Pavel Cicák. 73-80 [doi]
• A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant ApplicationsArvin Delavari, Faraz Ghoreishy, Hadi Shahriar Shahhoseini, Sattar Mirzakuchaki. 81-89 [doi]
• APEnetX: A Custom NIC for Cluster InterconnectsRoberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Luca Pontisso, Cristian Rossi, Francesco Simula, Piero Vicini. 90-97 [doi]
• FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued CrossbarKlajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf. 98-105 [doi]
• Achieving High Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGAJonas Ney, Norbert Wehn. 106-113 [doi]
• A Hardware Accelerator for Quantile Estimation of Network Packet AttributesCarolina Gallardo-Pavesi, Yaime Fernández, Javier E. Soto, Cecilia Hernández, Miguel E. Figueroa. 114-121 [doi]
• Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural ReceiversBram Van Bolderik, Souradip Sarkar, Vlado Menkovski, Sonia Heemstra, Manil Dev Gomony. 122-128 [doi]
• How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 MicrocontrollerLukás Danêk, Martin Novotný. 129-136 [doi]
• Securing Elapsed Time for Blockchain: Proof of Hardware Time and Some of its Physical ThreatsQuentin Jayet, Christine Hennebert, Yann Kieffer, Vincent Beroulle. 137-144 [doi]
• Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAsShree Harish S, Debapriya Basu Roy. 145-152 [doi]
• Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES CipherFrancisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Virginia Zúñiga-González, A. J. Acosta. 153-160 [doi]
• Teaching Agile Hardware Design with ChiselScott Beamer. 161-167 [doi]
• Hardware Generators with ChiselMartin Schoeberl, Hans Jakob Damsgaard, Luca Pezzarossa, Oliver Keszöcze, Erling Rennemo Jellum. 168-175 [doi]
• DSL-Based SNN Accelerator Design Using ChiselPatrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze. 176-184 [doi]
• ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet TrafficFranz Biersack, Marco Liess, Markus Absmann, Fabiana Lotter, Thomas Wild, Andreas Herkersdorf. 185-193 [doi]
• Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic ClassificationJulio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 194-201 [doi]
• CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on VideoDaniel Suárez, Víctor Fernández 0001, Héctor Posadas. 202-209 [doi]
• PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event DataDominika Przewlocka-Rus, Tomasz Kryjak, Marek Gorgon. 210-217 [doi]
• Two's Complement: Monitoring Software Control Flow Using Both Power and Electromagnetic Side ChannelsMichael Amar, Lojenaa Navanesan, Asanka P. Sayakkara, Yossi Oren. 218-226 [doi]
• An HLS Algorithm for the Direct Synthesis of Complex Control Flow Graphs Into Finite State Machines with Implicit DatapathJean-Christophe Le Lann. 227-233 [doi]
• Integrated Mapping and Scheduling Optimization with Genetic Algorithms Based on a Novel Encoding SchemeZhifang Sun, Shengjie Jin, Jinxue Duan, Junqiang Jiang, Zebo Peng. 234-241 [doi]
• SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAsChristie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy. 242-249 [doi]
• Streamlined Models of CMOS Image Sensors Carbon ImpactsOlivier Weppe, Jérôme Chossat, Thibaut Marty, Jean-Christophe Prévotet, Maxime Pelcat. 250-257 [doi]
• HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers FrameworkSaketh Gajawada, Dantu Nandini Devi, Madhav Rao. 258-265 [doi]
• Exploration of Custom Floating-Point Formats: A Systematic ApproachSaba Yousefzadeh, Yu Yang, Astile Peter, Dimitrios Stathis 0001, Ahmed Hemani. 266-273 [doi]
• Hardware-level Access Control and Scheduling of Shared Hardware AcceleratorsCornelia Wulf, Sergio A. Pertuz 0001, Diana Göhringer. 274-281 [doi]
• Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+Alejandro Serrano-Cases, Enrico Mezzetti, Jaume Abella 0001, Francisco J. Cazorla. 282-290 [doi]
• Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18Zhuoer Li, Sébastien Bilavarn. 291-297 [doi]
• Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case StudyFelipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner. 298-305 [doi]
• SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing SystemsLuca Zulberti, Andrea Monorchio, Matteo Monopoli, Gabriela Mystkowska, Pietro Nannipieri, Luca Fanucci. 306-313 [doi]
• Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-EngineGabriela Mystkowska, Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci. 314-318 [doi]
• AUTOSAR AP and ROS 2 Collaboration FrameworkRyudai Iwakami, Bo Peng, Hiroyuki Hanyu, Tasuku Ishigooka, Takuya Azumi. 319-326 [doi]
• Multiprotocol Middleware Translator for IoTBernando Cabral, Ricardo Venâncio, Pedro Costa, Tiago Fonseca, Luis Lino Ferreira, Ricardo Severino, António Barros. 327-334 [doi]
• Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including AutovectorizationPhilipp van Kempen, Mathis Salmen, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 335-342 [doi]
• Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUsNoïc Crouzet, Thomas Carle, Christine Rochange. 343-350 [doi]
• A Suite of Processors to Explore CHERI-RISC-V Micro ArchitecturePeter Rugg, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore. 351-360 [doi]
• Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP DisclosureCan Aknesil, Elena Dubrova. 361-368 [doi]
• Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability AssessmentPensec William, Lapôtre Vianney, GOGNIAT Guy. 369-376 [doi]
• Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path ActivationsGeorgios Anagnostopoulos, Nikolaos Zompakis, Sotirios Xydis. 377-384 [doi]
• External Memory Protection on FPGA-Based Embedded SystemsJoão Carlos Resende, Aleksandar Ilic, Ricardo Chaves. 385-393 [doi]
• Event Monitor Validation in High-Integrity SystemsRoger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan 0002, Jaume Abella 0001, Francisco J. Cazorla. 394-402 [doi]
• Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCsMatthias Stammler, Florian Schade, Jürgen Becker 0001. 403-409 [doi]
• DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the EdgeEnsieh Aliagha, Najdet Charaf, Nitin Krishna Venkatesan, Diana Göhringer. 410-417 [doi]
• Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini AcceleratorFederico Nicolás Peccia, Svetlana Pavlitska, Tobias Fleck, Oliver Bringmann 0001. 418-426 [doi]
• PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue DetectionSima Sinaei, Mohammadreza Mohammadi, Rakesh Shrestha, Mina Alibeigi, David Eklund. 427-434 [doi]
• 6G-TakeOff: Holistic 3D Networks for 6G Wireless CommunicationsMarko S. Andjelkovic, Nebojsa Maletic, Nicola Miglioranza, Milos Krstic, Enrico Koeck, Jan Buchholz, Maike Taddiken, Markus Fehrenz, Shaden Baradie, Dirk Wübben, Markus Breitbach. 435-442 [doi]
• 3D Decision Support Tool for Brain Tumour Surgery: The STRATUM ProjectHimar Fabelo, Raquel León, Emanuele Torti, Santiago Marco, Max Verbers, Yann Falevoz, Yolanda Ramallo-Fariña, Christian Weis, Ana M. Wägner, Eduardo Juárez Martínez, Claudio Rial, Alfonso Lagares, Gustav Burström, Francesco Leporati, Elisa Marenzi, Teresa Cervero, Miquel Moretó, Giovanni Danese, Sveta Zinger, Francesca Manni, Maria Luisa Alvarez-Male, Jesús Morera, Bernardino Clavo, Gustavo Marrero Callicó, Stratum Consortium. 443-450 [doi]
• REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for Safe and Secure AIAndreas Brokalakis, Iakovos Mavroidis, Konstantinos Georgopoulos, Pavlos Malakonakis, Konstantinos Harteros, Dimitris Andronikou, Yannis Galanomatis, Charalampos Savvakos, Grigorios Chrysos 0001, Sotiris Ioannidis, Ioannis Papaefstathiou. 451-456 [doi]
• Assessment of the Performance of a Commercial Spectral Sensor for Portable and Cost-Effective Multispectral ApplicationsAntonio J. Pérez-Ávila, Miguel A. Mesa-Simón, Antonio Martínez-Olmos, Alberto J. Palma, Nuria López-Ruiz. 457-463 [doi]
• Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition SystemsLaura Quintana, Carlos Vega, Raquel León, Guillermo V. Socorro-Marrero, Samuel Ortega, Gustavo Marrero Callicó. 464-471 [doi]
• Inter-Band Movement Compensation Method for Hyperspectral Images Based on Spectral Scanning TechnologyNerea Marquez-Suarez, Carlos Vega, Raquel León, Gustavo Marrero Callicó. 472-479 [doi]
• HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB ImagesMarco Gazzoni, Emanuele Torti, Elisa Marenzi, Giovanni Danese, Francesco Leporati. 480-486 [doi]
• Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML ModelsMounika Vaddeboina, Alper Yilmayer, Wolfgang Ecker. 487-494 [doi]
• LeQC-At: Learning Quantization Configurations During Adversarial Training for Robust Deep Neural NetworksSiddharth Gupta 0004, Salim Ullah, Akash Kumar 0001. 495-502 [doi]
• High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAsYan Chen 0029, Kiyofumi Tanaka. 503-511 [doi]
• HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No CostBailian Sun, Mohamed Hassan 0002. 512-520 [doi]
• Digital Twins Benefits and Challenges from Intelligent Motion Control Point of ViewMatias Vierimaa, Mikko Heiskanen, Sajid Mohamed, Hans Kuppens. 521-525 [doi]
• The TEXTAROSSA Project: Cool all the Way Down to the HardwareAntonio Filgueras, Giovanni Agosta, Marco Aldinucci, Carlos Álvarez 0001, Pasqua D'Ambra, Massimo Bernaschi, Andrea Biagioni, Daniele Cattaneo 0002, Alessandro Celestini, Massimo Celino, Carlotta Chiarini, Francesca Lo Cicero, Paolo Cretaro, William Fornaciari, Ottorino Frezza, Andrea Galimberti, Francesco Giacomini, Juan Miguel De Haro Ruiz, Francesco Iannone, Daniel Jaschke, Daniel Jiménez-González, Michal Kulczewski, Alberto Leva, Alessandro Lonardo, Michele Martinelli, Xavier Martorell, Simone Montangero, Lucas Morais, Ariel Oleksiak, Paolo Palazzari, Luca Pontisso, Federico Reghenzani, Cristian Rossi, Sergio Saponara, Carlo Saverio Lodi, Francesco Simula, Federico Terraneo, Piero Vicini, Miquel Vidal, Davide Zoni, Giuseppe Zummo. 526-533 [doi]
• SAND5G - Security Assessments for Networks and Services in 5G NetworksAimilia Bantouna, Kostas Lampropoulos 0001, Omar Qaise, Andreas Stamoulis, Paris Kitsos, Kostas Poulios, Lampros Raptis, Christos Tranoris. 534-540 [doi]
• Event-Based Vision on FPGAs - a SurveyTomasz Kryjak. 541-550 [doi]
• An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite ImageryCornell Castelino, Shashwat Khandelwal, Shanker Shreejith, Sharatchandra Varma Bogaraju. 551-558 [doi]
• TAP: Task-Aware Profiling on Integrated SystemsJeremy Giesen, Enrico Mezzetti, Jaume Abella 0001, Francisco J. Cazorla. 559-567 [doi]
• Precision and Power Efficient Piece-Wise-Linear Implementation of Transcendental FunctionsKanish R, Omkar G. Ratnaparkhi, Madhav Rao. 568-575 [doi]
• Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory PianistsRens Baeyens, Max Cornilly, Dennis Laurijssen, Ron Clijsen, Jean-Pierre Baeyens, Jan Steckel, Walter Daems. 576-581 [doi]
• In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate LocalizationPaola Vitolo, Gian Domenico Licciardo, Danilo Pau, Rosalba Liguori, Luigi Di Benedetto, Alfredo Rubino. 582-587 [doi]
• FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI ProcessingDomenico Ragusa, Antonio J. Rodríguez-Almeida, Marco Gazzoni, Emanuele Torti, Elisa Marenzi, Himar Fabelo, Gustavo Marrero Callicó, Francesco Leporati. 588-595 [doi]
• Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGADaniel Enériz, Antonio J. Rodríguez-Almeida, Himar Fabelo, Gustavo Marrero Callicó, Nicolás Medrano, Belén Calvo. 596-603 [doi]
• The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of ThingsJakub Lojda, Josef Strnadel, Václav Simek, Pavel Smrz, Mike Hayes, Ralf Popp. 604-611 [doi]
• The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware AcceleratorsAlejandro J. Calderón, Aitor Amonarriz, Mar Hernández, Leonidas Kosmidis, Jannis Wolf, Marc Solé Bonet, Matina Maria Trompouki, Mikel Segura, Peio Onaindia. 612-619 [doi]
• Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust ProjectHassan Aboushady, Noemie Beringuier-Boher, Kelly Burke, Philippe Dallemagne, Mario De Biase, Manuel Di Frangia, Virginie Deniau, Enrico Ferrari, Christophe Gaquière, Dominique Morche, Fabio Patrone, Stefano Pesci, Luigi Pomante, Andries Stam, Vincenzo Stornelli, Haralampos-G. Stratigopoulos, Mottaqiallah Taouil, Emmanuel Vaumorin, Jonathan Villain, Sander Steeghs. 620-627 [doi]