Sébastien Bilavarn - researchr alias

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Viewing Publication 1 - 16 from 16

2022

Synaptic Activity and Hardware Footprint of Spiking Neural Networks in Digital Neuromorphic SystemsEdgar Lemaire, Benoît Miramond, Sébastien Bilavarn, Hadi Saoud, Nassim Abderrahmane. tecs, 21(6), November 2022. [doi]

Efficiency analysis of artificial vs. Spiking Neural Networks on FPGAsZhuoer Li, Edgar Lemaire, Nassim Abderrahmane, Sébastien Bilavarn, Benoît Miramond. jsa, 133:102765, 2022. [doi]

2020

An FPGA-Based Hybrid Neural Network Accelerator for Embedded Satellite Image ClassificationEdgar Lemaire, Matthieu Moretti, Lionel Daniel, Benoît Miramond, Philippe Millet, Frédéric Feresin, Sébastien Bilavarn. iscas 2020: 1-5 [doi]

2018

Modélisation, Conception Système d'Architectures Hétérogènes pour les Applications Embarquées : Eléments d'amélioration de l'efficacité énergétique des systèmes sur puce de silicium. (Modelling, Design of Heterogenous architectures for embedded Applications / Modelling, Design of Heterogenous architectures for embedded Applications : Refinement parts about power efficiency of silicon chips systems)Sébastien Bilavarn. 2018. [doi]

Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart cameraRobin Bonamy, Sébastien Bilavarn, Fabrice Muller, François Duhem, Simon Heywood, Philippe Millet, Fabrice Lemonnier. ijcta, 46(9):1648-1662, 2018. [doi]

2017

Efficiency modeling and exploration of 64-bit ARM compute nodes for exascaleJoel Wanza Weloli, Sébastien Bilavarn, Maarten de Vries, Said Derradji, Cécile Belleudy. mam, 53:68-80, 2017. [doi]

2016

2015

An energy-aware scheduler for dynamically reconfigurable multi-core systemsRobin Bonamy, Sébastien Bilavarn, Fabrice Muller. recosoc 2015: 1-6 [doi]

HLS based design of a mixed architecture for H.264/AVC CAVLDTaheni Damak, Sébastien Bilavarn, Nouri Masmoudi. IEEEssd 2015: 1-4 [doi]

FoRTReSS: a flow for design space exploration of partially reconfigurable systemsFrançois Duhem, Fabrice Muller, Robin Bonamy, Sébastien Bilavarn. dafes, 19(3):301-326, 2015. [doi]

2012

Impact of operating points on DVFS power managementJabran Khan, Sébastien Bilavarn, Cécile Belleudy. dtis 2012: 1-6 [doi]

2008

UML profile for estimating application Worst Case Execution Time on System-on-ChipFateh Boutekkouk, Sébastien Bilavarn, Michel Auguin, Mohammed Benmohammed. issoc 2008: 1-6 [doi]

2002

Exploration Architecturale au Niveau Comportemental - Application aux FPGAs. (Architectural Exploration in behavioral level - Application to FPGAs)Sébastien Bilavarn. PhD thesis, University of Southern Brittany, Morbihan, France, 2002. [doi]

2000

Area time power estimation for FPGA based designs at a behavioral levelSébastien Bilavarn, Guy Gogniat, Jean Luc Philippe. icecsys 2000: 524-527 [doi]

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