Table of Contents

• Predictable photonic interconnects using an autonomous channel management and a TDMA-NoCWolfgang Buter, Christof Osewold, Awais Ahmed, Daniel Gregorek, Alberto García Ortiz. 1-6 [doi]
• Execution modeling in self-aware FPGA-based architectures for efficient resource managementAlfonso Rodriguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo. 1-8 [doi]
• Envisioning self-verification of electronic systemsRolf Drechsler, Martin Fränzle, Robert Wille. 1-6 [doi]
• Automated composition and execution of hardware-accelerated operator graphsStefan Werner, Dennis Heinrich, Jannik Piper, Sven Groppe, Rico Backasch, Christopher Blochwitz, Thilo Pionteck. 1-8 [doi]
• Configurable cache tuning with a victim cacheOsvaldo Navarro, Tim Leiding, Michael Hübner. 1-6 [doi]
• Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generationStefan Gehrer, Georg Sigl. 1-6 [doi]
• Message from the chairsAlberto García Ortiz, Daniel Gregorek, Eduardo de la Torre, Juha Plosila. 1 [doi]
• Reconfigurable Vector Extensions inside the DRAMMarco Antonio Zanata Alves, Paulo C. Santos, Matthias Diener, Luigi Carro. 1-6 [doi]
• An energy-aware scheduler for dynamically reconfigurable multi-core systemsRobin Bonamy, Sébastien Bilavarn, Fabrice Muller. 1-6 [doi]
• + tree in a Semantic Web database systemDennis Heinrich, Stefan Werner, Marc Stelzner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe. 1-8 [doi]
• Beyond many-core: Commercial workload acceleration in high-end systemsCédric Lichtenau. 1 [doi]
• A decentralised, autonomous, and congestion-aware thermal monitoring infrastructure for photonic network-on-chipWolfgang Buter, Yanqiu Huang, Daniel Gregorek, Alberto García Ortiz. 1-8 [doi]
• Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAsJavier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo. 1-7 [doi]
• S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCsZahra Shirmohammadi, Seyed Ghassem Miremadi. 1-6 [doi]
• On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAsBoyang Du, Luca Sterpone, Lorenzo Venditti, David Merodio Codinachs. 1-6 [doi]
• A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applicationsCharlotte Frenkel, Jean-Didier Legat, David Bol. 1-7 [doi]
• FPGA based traffic sign detection for automotive camera systemsFynn Schwiegelshohn, Lars Gierke, Michael Hübner. 1-6 [doi]
• Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-ChipYunfeng Ma, Leandro Soares Indrusiak. 1-8 [doi]
• A survey on security features in modern FPGAsRémy Druyer, Lionel Torres, Pascal Benoit, Paul-Vincent Bonzom, Patrick Le-Quéré. 1-8 [doi]
• Energy efficient 3D Hybrid processor-memory architecture for the dark silicon ageSobhan Niknam, Arghavan Asad, Mahmood Fathy, Amir-Mohammad Rahmani. 1-8 [doi]
• Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCsByron Navas, Ingo Sander, Johnny Öberg. 1-8 [doi]
• A flexible co-processing approach for SoC-FPGAs based on dynamic partial reconfiguration and bitstream relocation methodsTimm Friedrich, Kurt Franz Ackermann. 1-7 [doi]
• Towards run-time flexible risk management systems on hybrid platformsChristian de Schryver. 1 [doi]
• Reconfigurable communication fabric for efficient implementation of neural networksArash Firuzan, Mehdi Modarressi, Masoud Daneshtalab. 1-8 [doi]
• A framework for remote and adaptive partial reconfiguration of SoC based data acquisition systems under LinuxA. Amalin Prince, Vineeth Kartha. 1-5 [doi]
• Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCsJohanna Sepúlveda, Daniel Florez, Guy Gogniat. 1-8 [doi]
• Design to surviveSergio Montenegro. 1 [doi]
• A framework for hardware-based DVFS management in multicore mixed-criticality systemsParham Haririan, Alberto García Ortiz. 1-7 [doi]
• Using hardware parallelism for reducing power consumption in video streaming applicationsKarim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser. 1-7 [doi]
• Automated minimization of concurrent online checkers for Network-on-ChipsPietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein. 1-8 [doi]
• Mixed-criticality NoC partitioning based on the NoCDepend dependability techniqueThomas Hollstein, Siavoosh Payandeh Azad, Thilo Kogge, Behrad Niazmand. 1-8 [doi]
• Emulation of an ASIC power and temperature monitor system for FPGA prototypingElisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel. 1-8 [doi]