Table of Contents

• Large Language Models for Printed Circuit Board Test GenerationAlbin Lidbäck, Erik Larsson. 1-2 [doi]
• Embedded Tutorial: Integrated System Hardening Seen from a Security Point of View: Dream or Nightmare?Régis Leveugle. 1-4 [doi]
• DOC: Detection of On-Line Failures in CNNsVittorio Turco, Nicolò Bellarmino, Annachiara Ruospo, Riccardo Cantoro, Ernesto Sánchez 0001. 1-6 [doi]
• A Combined Strategy for Testing RRAMs After Manufacturing and During LifetimeThiago Santos Copetti, Supriya Chakraborty, Letícia Maria Bolzani Poehls. 1-6 [doi]
• About the Functional In-Field Self-Testing of AI AcceleratorsJuan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Robert Limas Sierra, Matteo Sonza Reorda. 1-6 [doi]
• IoT and Edge Computing: Applications and Reliability ImplicationsEdward-W. Caro-Anzola, Giuseppe Esposito, Juan-David Guerrero-Balaguera, Andrés Jiménez López, Fabián-R. Jiménez-López, Robert Limas Sierra, Gustavo Ramirez Espinosa, Edoardo Giusto, Bartolomeo Montrucchio, Oscar-F. Vera-Cely, Josie E. Rodriguez Condia. 1-10 [doi]
• Case Study: AI-Driven Log Extraction and Trace Outlier Detection for Efficient Post-Silicon ValidationKowshic A. Akash, Tobias Wulf, Torsten Valentin, Alexander Geist, Ulf Kulau, John Jose, Sohan Lal. 1-4 [doi]
• Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous QuantizationSamira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Christian Herglotz, Maksim Jenihhin. 1-6 [doi]
• Analysis of Voltage Drop and Temperature Effects on Harmonic Errors Under EMFI on ROsSami El Amraoui, Luc Salvo, Régis Leveugle, Paolo Maistri. 1-6 [doi]
• Bi-LORD: Bit-Wise Low-Cost Real Numbers Dependability Assessment in AI ApplicationsJulia Azziz, Annachiara Ruospo, Ernesto Sánchez 0001, Julio Pérez Acle. 1-6 [doi]
• Generation of Simulated Neutrino Signals for the Digitization Subsystem in the DAPHNE Test Bench of the DUNE ExperimentValentina Ródriguez, Jerónimo López, Juan Fajardo, Valentina Restrepo, Fabián Andrés Castaño. 1-6 [doi]
• Robust DLBIST for Delay Fault Testing: Minimizing PVT Variability with Zero Temperature Coefficient (ZTC) VoltageHanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich. 1-6 [doi]
• Case Study: NASCERR: In-Mission Self-Tuning Error Correction Approach for Space ApplicationsLucas De Albuquerque, Clara Luz Salles Cavalcante, Danilo Alencar, Eléna Mallet De Chauny Druesne, João Manoel Matos Sobreira, Marcus Anderson Almeida Bezerra, Alexandre Almeida da Silva, José Edilson Silva Filho, Jarbas Silveira, Fabian Luis Vargas 0001. 1-4 [doi]
• Special Session: D-MATE: A Design Methodology for Connecting Automatic Test Equipment in Industry 4.0Francesco Biondani, Francesco Tosoni 0002, Nicola Dall'Ora, Enrico Fraccaroli, Sara Vinco, Dong Seon Cheng, Franco Fummi. 1-6 [doi]
• 28 nm FD-SOI 4 K RF LNA Design Using DC Transistor Characterization MeasurementsGiovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mickael Casse, Philippe Galy. 1-6 [doi]
• Approximate Analytical Model Evaluating Digital Systems Compliance with Automotive StandardsEsther Goudet, Fabio Sureau, Manan Kaila, Rémi Germe, Luis Peña Treviño, Jean-Marc Daveau, Lirida Naviner, Philippe Roche. 1-6 [doi]
• Enhancing Logic Diagnosis of Field Returns Through Logic BIST in Automotive SoCsPaolo Bernardi, Gabriele Filipponi, Giusy Iaria, Claudia Bertani, Vincenzo Tancorre. 1-6 [doi]
• Zero-Day Hardware-Supported Malware Detection of Stack Buffer Overflow Attacks: An Application Exploiting the CV32e40p RISC-V CoreCristiano Pegoraro Chenet, Alessandro Savino, Stefano Di Carlo. 1-6 [doi]
• IoT-Based Digital Twin for Vehicle Battery Testing and Emissions AnalysisGeorge Flutur, Ovidiu Petru Stan, Gabriel Chindris, Liviu Cristian Miclea. 1-6 [doi]
• Impact of Thermal Effects on Cryptographic Resilience: A Study of an ASIC Implementation of the Montgomery LadderIevgen Kabin, Peter Langendoerfer, Zoya Dyka. 1-4 [doi]
• UNApprox: An Open-Source Tool for Loop Perforation in Approximate ComputingAlexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Pedraza Bonilla. 1-6 [doi]
• Investigating Manufacturing Defects Leading to Potential Silent Data ErrorsJorge Lopez, Víctor H. Champac. 1-6 [doi]
• On-Chip Aging Sensor Core for Silicon Lifecycle ManagementFabian Vargas 0001, Aneesh Balakrishnan. 1-6 [doi]
• Double Column Error Correction in RRAM Matrix Multiplication Using Weighted ChecksumsKrishnaja Kodali, Kenrick Xavier Pinto, Abhishek Das, Nur A. Touba. 1-6 [doi]
• Special Session: A Model-Driven Design Tool for Modelling, Simulation and Assertion-Based Verification of Hybrid AutomataDaniele Nicoletti, Samuele Germiniani, Alessandro Aldegheri, Michele Cipriani, Davide Venturi, Tommaso Vilotto, Graziano Pravadelli. 1-6 [doi]
• Zero Overhead Error-Tolerant CommunicationSomayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich. 1-6 [doi]
• Preserving and Improving Verifiability of Circuits Based on Local TransformationsRolf Drechsler. 1-2 [doi]
• Estimating the Impact of Soft Errors on AI-Based Perception in AutomotiveShailesh Hegde, Dinesh Cyril Selvaraj, Josie E. Rodriguez Condia, Nicola Amati, Carla-Fabiana Chiasserini, Francesco Deflorio, Matteo Sonza Reorda. 1-6 [doi]
• Grouped Feature Selection for SMONs Placement in MCU Performance ScreeningNicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Giovanni Squillero. 1-6 [doi]
• Improving CNN Runtime Robustness Against Soft Errors by Dropout Layer OptimizationRobert Limas Sierra, Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 1-6 [doi]
• Case Study: UVM-FIE: Enhancing UVM-Based Fault Injection Library for Complex DesignsLeonardo S. Tavares, Wang J. Chau, Fernando J. Fonseca. 1-4 [doi]
• Leveraging ATE to Optimize System-Level-Test for Multicore Automotive SoCsFrancesco Angione, Paolo Bernardi, Claudia Bertani, Lorenzo Bertetto, Lorenzo Cardone, Nicola Di Gruttola Giardino, Stefano Quer, Vincenzo Tancorre. 1-6 [doi]
• Image Test Libraries for the In-Field Test of Ultra-Low-Power DevicesAntonio Porsia, Giacomo Perlo, Annachiara Ruospo, Ernesto Sanchez. 1-6 [doi]
• Case Study: Horizontal Side-Channel Analysis Attack Against Elliptic Curve Scalar Multiplication Accelerator Under Laser IlluminationDmytro Petryk, Ievgen Kabin, Peter Langendoerfer, Zoya Dyka. 1-4 [doi]
• Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL LevelBehnam Farnaghinejad, Antonio Porsia, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Sánchez 0001. 1-2 [doi]