Table of Contents

• Quantitative Evaluation on the Limits of SORN Arithmetic Hardware CircuitsMoritz Bärthel, Nils Hülsmeier, Jochen Rust, Steffen Paul. 1-5 [doi]
• AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded ApplicationsAhmad Othman, Ahmed Kamaleldin, Diana Göhringer. 1-7 [doi]
• Design of Single-Bit Switched-Capacitor ΔΣ Modulators Employing Fast-Settling TechniquesAlessandro Catania, Francesco Gagliardi 0002, Michele Dei. 1-7 [doi]
• Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces TestbedMikael Henriksson, Hugo Winbladh, Oscar Gustafsson. 1-6 [doi]
• On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction MemoryJohn Reuben, Suzanne Lancaster, Dietmar Fey, Stefan Slesazeck. 1-6 [doi]
• Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting SystemsAndré F. Ponchet, Javad Bagheri Asli, Alireza Saberkari, César W. V. Casañas, Atila Alvandpour, Ingemar Söderquist, Osamu Saotome. 1-6 [doi]
• Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-LinkVida Sobhani, Jan Lorenz, Tobias Gemmeke. 1-7 [doi]
• Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time SystemsAntti Nurmi, Abdesattar Kalache, Timo D. Hämäläinen. 1-6 [doi]
• VLSI integration of a RO-based PUF into a 65 nm technologyPau Ortega-Castro, Felipe Rojas-Muñoz, José Miguel Mora-Gutiérrez, Piedad Brox, Macarena C. Martínez-Rodríguez. 1-7 [doi]
• Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary AlgorithmsJulian Haase, Najdet Charaf, Alexander Groß 0002, Diana Göhringer. 1-7 [doi]
• A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested LoopsRg Raghavendra, Kamlesh Singh, Milind Gopal Agrawal. 1-7 [doi]
• Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device TrainingJosé L. Núñez-Yáñez. 1-7 [doi]
• Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional NetworksOlle Hansson, Oscar Gustafsson, José L. Núñez-Yáñez. 1-7 [doi]
• QoS-Aware Dynamic Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement LearningFlorian Maurer 0003, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf. 1-6 [doi]
• ZuSE-KI-Mobil AI Chip Design Platform: An OverviewShaown Mojumder, Simon Friedrich, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Julian Höfer, Patrick Schmidt, Jürgen Becker 0001, Darius Grantz, Markus Kock, Jens Benndorf, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Kay Bierzynski. 1-7 [doi]
• A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCsAbolfazl Sajadi, Nusa Zidaric, Todor Stefanov, Nele Mentens. 1-7 [doi]
• Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing ApproachesSebastian Jaster, Julian Haase, Diana Göhringer, Elke Franz 0001. 1-7 [doi]
• FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSDRashed Al Amin, Roman Obermaisser. 1-5 [doi]
• Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and BeyondMayuri Bhadra, Stephanie Ecker, Daniel Albert, Ravindra Ramaiah, Sebastian Prebeck, Wolfgang Ecker. 1-7 [doi]
• MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS TechnologyMd Najmussadat, Y. Tawfik, R. Ahamed, Mikko Varonen, Dristy Parveg, Antti Lamminen, Pekka Pursula, Kari A. I. Halonen. 1-5 [doi]
• Towards a General Compilation Approach for On-device Training in Embedded SystemsIuliia Topko, Tanja Harbaum, Jürgen Becker 0001. 1-7 [doi]
• Exploiting SORN-Arithmetic for Efficient Cross Correlation in Low-Complexity FPGAsJochen Rust, Marvin Henkel, Nils Hülsmeier, Moritz Bärthel, Steffen Paul. 1-5 [doi]
• Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-CorrectionOliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic. 1-4 [doi]
• Enhanced Mixer-First Receiver Using Series Switch N-Path Passive Mixer for Millimeter-Wave 5G ApplicationsFatemeh Abbassi, Timm Ostermann, Christoph Wagner. 1-5 [doi]
• Cycle Count Estimation of VLIW Processors Using Machine LearningKari Hepola, Jatan Shrestha, Joonas Multanen, Vivienne Wang, Joni Pajarinen, Pekka Jääskeläinen. 1-7 [doi]
• On the Optimal Design of Integrated AC-DC Converters for Energy HarvestingLuca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua. 1-6 [doi]
• An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge AccumulationKimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai. 1-6 [doi]
• Compact and Efficient Switching Power Amplifier for Micro-NMR ApplicationsMohammed Al Shihabi, Natachai Terawatsakul, Alireza Saberkari. 1-6 [doi]
• FPGA-Based Hardware Acceleration for Deep Learning in Mobile RoboticsYasir Al-Ameri, Ming Nguyen, Tomi Westerlund. 1-7 [doi]
• Hardware-accelerated Compression Core on RISC-V for Online-BCG Data ReductionKazi Mohammad Abidur Rahman, Abdelrahman Noshy Abdelalim Ahmed, Görschwin Fey, Ulf Kulau. 1-6 [doi]
• Indoor Positioning using Distributed MIMO: Processing Architecture and FPGA ImplementationDumitra Iancu, Lina Tinnerberg, Ove Edfors, Liang Liu 0002. 1-6 [doi]
• High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH ApplicationsWei Cao, Alireza Saberkari, Atila Alvandpour. 1-6 [doi]
• 2 1.2V 0.089pJ/bit 10Gbps 41.6 GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFETHiroaki Kitaike, Hironori Tagawa, Masaya Kaneko, Jin Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hiroki Wakatsuchi, Kyoya Takano, Hirofumi Shinohara, Kiichi Niitsu. 1-6 [doi]
• RISC-V Triplet: Tapeouts for Security ApplicationsJonas Schupp, Patrick Karl, Jens Nöpel, Alexander Hepp, Tim Music, Georg Sigl. 1-6 [doi]
• Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded SystemsPablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox. 1-7 [doi]
• Highly linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensorBelal Mostafa Amin, Ilkka Nissinen. 1-6 [doi]
• Novel Circuit for In-Memory Computing within STT-RAM Memory BlocksPegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi, Hooman Farkhani. 1-6 [doi]
• A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM InterfacesMohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn. 1-6 [doi]
• Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional NetworksHadi Mousanejad Jeddi, Mahdieh Grailoo, José L. Núñez-Yáñez. 1-7 [doi]
• Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom InstructionsKari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen. 1-7 [doi]
• On the Efficiency Enhancement of Voltage Mode Digital Doherty Power AmplifiersEdoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua. 1-5 [doi]
• Towards modularity of the Rust RTIC real-time scheduling frameworkZakaria Madaoui, Henri Lunnikivi, Pawel Dzialo, Per Lindgren. 1-7 [doi]
• Implementation of the Tagged Geometric History Length Access Interval PredictorViktor Razilov, Emil Matús, Gerhard P. Fettweis. 1-4 [doi]
• RV-ProViler: Evaluating RISC-V ISA for Application-Specific RequirementsMuhammad Ali 0010, Ensieh Aliagha, Mahmoud Elnashar, Diana Göhringer. 1-7 [doi]
• Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge PlatformMahdieh Grailoo, Tooraj Nikoubin, José L. Núñez-Yáñez. 1-6 [doi]
• 2 65 nm CMOS Multiple- Output Down-Converter-Less Clock Generator Using Stacked an Oscillator and Frequency Dividers for Scaling-Friendly IoTsYou Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu. 1-6 [doi]
• Tywaves: A Typed Waveform Viewer for ChiselRaffaele Meloni, H. Peter Hofstee, Zaid Al-Ars. 1-6 [doi]
• Trustworthy Silicon: An MPSoC for a Secure Operating SystemSebastian Haas, Christopher Dunkel, Friedrich Pauls, Mattis Hasler, Yogesh Verma. 1-7 [doi]
• A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCsMoritz Weißbrich, Alexander Meyer, Adilet Dossanov, Vadim Issakov, Guillermo Payá Vayá. 1-6 [doi]
• Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference TimesFabian C. Legl, Jonas Kantic. 1-7 [doi]
• Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case StudyMohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri. 1-7 [doi]
• Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level SynthesisSergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee. 1-7 [doi]