Table of Contents

• 2 Digital Compute-in-Memory Macro with a Novel 6T+MUX Bitcell for Sparsity-Aware MAC OperationsPriyanshu Tyagi, Aayush Gautam, Sparsh Mittal. 1-6 [doi]
• An FPGA-Based Secure and Privacy-Aware RISC-V SoC with a CNN Accelerator for Edge AIPriyanshu Tyagi, Rhythm Patel, Sparsh Mittal, Rekha Singhal. 7-12 [doi]
• Bipolar Silicon Synapse for Bidirectional Spiking Neural NetworksTamal Chowdhury, Pradip Mandal. 13-18 [doi]
• Design and FPGA Implementation of Power and Area Efficient Multi-Stage Accelerator for Depthwise Separable ConvolutionsSrishti Misra, Rahul Shrestha. 19-24 [doi]
• PolyEMAC: Polynomial Error Metrics Analysis in Approximate ComputingMohamed A. Nadeem, Chandan Kumar Jha 0001, Rolf Drechsler. 25-30 [doi]
• A Novel VLSI Architecture and FPGA Implementation of Hardware-Efficient Mfocuss-Based Wideband Spectrum Sensor for Dynamic Spectrum AccessAayush Shrivas, Rahul Shrestha. 31-36 [doi]
• XR-NPE: High-Throughput Mixed-Precision SIMD Neural Processing Engine for Extended Reality Perception WorkloadsTejas Chaudhari, Akarsh J, Tanushree Dewangan, Mukul Lokhande, Santosh Kumar Vishvakarma. 37-42 [doi]
• RAMAN: Resource-Efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-DesigNMohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma. 43-48 [doi]
• A Transistor-Level Implementation of Radix-2 and Radix-4 FFT Using Logical EffortHarsh Raj Thakur, Sparsh Mittal. 49-54 [doi]
• Thermal Runaway Analysis of Analog PIM AcceleratorsHuatao Wu, Sandip Kundu. 55-60 [doi]
• An Energy Efficient Pulse Accumulator Circuit (PAC) Based Multi-Bit Time Domain Compute in-Memory ArchitectureSubhradip Chakraborty, Dinesh Kushwaha. 61-66 [doi]
• A Forward-Backward Search Strategy for Falsification in Spiking Neural NetworksSruti Goswami, Ansuman Banerjee, Swarup Kumar Mohalik. 67-72 [doi]
• ASIC Design for a Hybrid Approximate Floating-Point Adder with Enhanced Carry Prediction LogicSridhar C, Aniruddha Kanhe. 73-78 [doi]
• PIDArc: Physics-Informed Deaggregated Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic CellsMohammad Rehan Akhtar, Zia Abbas. 79-84 [doi]
• PRISM: Photonic Reconfigurable In-Situ Memory for Next-Gen AI WorkloadsPratham Sharma, Santosh Kumar Vishvakarma. 85-90 [doi]
• Design and FPGA Implementation of a Wide-Range and Area-Efficient Programmable Frequency DividerShriniket Hemant Tare, Rohit Chaurasiya, Dron Sankhala, Chandan Yadav. 91-96 [doi]
• DIVIAC: Library of Input Data Aware Approximate Dividers with Partial Exact MinimizationChandan Kumar Jha 0001, Sallar Ahmadi-Pour, Sajjad Parvin, Rolf Drechsler. 97-102 [doi]
• Attack on a PUF-Based Secure Binary Neural NetworkBijeet Basak, Nupur Patil, Kurian Polachan, Srinivas Vivek 0001. 103-108 [doi]
• BHARAT-TPM: Micro-Architecture Design of Scalable Hardware Random Number Generator for a RISC-V Trusted Platform ModuleSoumya G. Hosmani, Raja Sekar K, Aneesh Raveendran, Vivian Desalphine, Haribabu P, S. D. Sudarsan. 109-114 [doi]
• DP-VSA: DSP Packing-Based Vector Systolic Accelerator with Dual Precision Support on FPGAsAashish Kumar Tiwary, Yathin Kumar Attuluri, Nanditha Rao. 115-120 [doi]
• A 2.95 pJ/b 42Gb/s PAM-8 Clock and Data RecoverySaurabh Saxena, Neel Hingrajiya, Suryadipto Mukherjee, Vivek Pala. 121-124 [doi]
• A Fully Reconfigurable and Adaptable Current-Source Based Sense Amplifier for Energy Efficient in-Memory ComputingParminder Kaur, Charagundla Sai Laxman, Amandeep Kaur. 125-130 [doi]
• All-Digital Ring Oscillator with Feature of Auto Frequency Tuning Using Serial DataHimanshu N. Patel, Chiragkumar Patel, Joycee Mekie, Hari Shankar Gupta, B. Saravana Kumar. 131-136 [doi]
• A 8-16 Gb/s/pin Full-Duplex Voltage-Mode Transmitter with Pulse Width Modulation Based Equalization and Analog Echo CancellerSaurabh Saxena, Vinod Ganesan, Shubham Choudhary. 137-142 [doi]
• LInC-BMC: A Lookahead Informed Clause Deletion Mechanism for Bounded Model CheckingSatyam Shubham, Sutirtha Bhattacharyya, Ansuman Banerjee, Raj Kumar Gajavelly. 143-148 [doi]
• MaSVet: A Flexible Framework for Statistical Modelling and Synthesis of Macroscopic Vehicular Trajectory DatasetsDipankar Mandal, Arnab Sarkar 0001, Arijit Mondal. 149-154 [doi]
• Balanced Cascade: Free-Flowing Microfluidic Lab-On-Chip for Generating Serial DilutionsTapalina Banerjee, Sudip Poddar, Bhargab B. Bhattacharya. 155-160 [doi]
• LeakAnalyser: Uncertainty-Aware Analysis of Leakage Power in Digital Circuits Under PVT VariationsSarang Kudtarkar, Zia Abbas. 161-166 [doi]
• HazeClear: A Hardware-Accelerated ASIC for Real-Time Video DehazingAvra Ghosh, Simontini Roy, Sayan Chattarjee, Sheli Sinha Chaudhuri. 167-172 [doi]
• AAMLA: An Autonomous Agentic Framework for Memory-Aware LLM-Aided Hardware GenerationRajat Bhattacharjya, Juhee Sung, Hangyeol Jung, Hyunwoo Oh, Arnab Sarkar 0001, Mohsen Imani, Nikil D. Dutt. 171-176 [doi]
• MPBMC: Multi-Property Bounded Model Checking with GNN-Guided ClusteringSoumik Guha Roy, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran. 179-184 [doi]
• Low-Power UART Architecture with Integrated SECDED for Reliable Asynchronous CommunicationVatsal Rathod, Jay Patel, Gunjan Thakur, Abhishek Ray 0004. 185-190 [doi]
• A Two-Bit Error Correction Protocol for Low-Power Serial Communication in IoT SystemsOm Maheshwari, Bikram Paul. 191-196 [doi]
• FPGA-Based 2-Phase Asynchronous Circuit Design for High Performance ComputingSuman Kalyan Porel, Subhadeep Nag, Hemanta Kumar Mondal, Aniruddha Chandra. 197-202 [doi]
• Modeling Supercapacitors for Longer Battery Life of Cardiac PacemakersSumanta Pyne. 203-208 [doi]
• CAD-Enabled pH Control Optimization for Digital Microfluidic Lab-on-ChipsSumanta Pyne, Bhargab B. Bhattacharya. 209-214 [doi]
• FPGA Optimized Pipelined Modulo Computation Architecture Leveraging Primitive Instantiation and Placement Constraints for Efficient Logic PackingSuprabhat Bhattacharjee, Ayan Palchaudhuri. 215-220 [doi]
• Temporal Data Encoding and On-Chip Training of an SNN for ECG ClassificationSaras Mani Mishra, Hanumant Singh Shekhawat, Gaurav Trivedi. 221-226 [doi]
• A 3nm Silicon Proven Mechanism to Eliminate Ground Bounce Impact for High-Precision Analog HVM Trim in Digital ProcessorsAnup J. Deka, Balabrahmachari Matcha, Sanjay Singh, Subbu Manam. 227-232 [doi]
• A Fast-Transient, Low Quiescent Controller on a 16nm Integrated Voltage RegulatorAnup J. Deka, Biswarup Rana, Shivansh Pandey, Shobhit Tyagi. 233-238 [doi]
• Mitigating Scan-Induced Vmin Failures Through Intelligent Test Optimization and Physical Design ImprovementsRatnadeep Dutta, Manish Pundir. 239-244 [doi]
• MIRAGE: Micro-Ring-Assisted General Engine with Phase-Error Compensation for Scalable Full-Range Matrix-Vector MultiplicationPriyabrata Dash, Dharanidhar Dang. 245-250 [doi]
• A Novel Temperature and Aging Invariant Voltage Droop Monitor Architecture with 96.94% AccuracyAnup J. Deka, Shobhit Tyagi, Manoja D. 251-256 [doi]
• A Polynomial Time Routing Algorithm for Meda Biochips Based on Dijkstra's AlgorithmIssei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama, Ankur Guputa. 257-262 [doi]
• A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical FunctionsAmogh K. M, Sunita M. S. 263-268 [doi]
• Leveraging XAI for Semiconductor Electrical - Parameter Characterization Using Machine LearningSiddhi Srivastava, Debojyoti Roy, Hriddhi Srivastava, Khushwant Sehra, Manoj Saxena. 269-274 [doi]
• A Low Noise CMOS Image Sensor with Column-Parallel ReadoutAmandeep Kaur 0005, Mukul Sarkar. 275-280 [doi]
• A 146 GOPS and 7.2 TOPS/W 6T SRAM-Based Analog CIM Macro Using Bit-Splitting for 8-Bit MAC OperationsCheena Singhal, Abhishek Goel, Sparsh Mittal, Sudeb Dasgupta. 281-286 [doi]
• Design of a Glitch-Free PLL with Asynchronous Feedback Divider Supporting Multiple Reference Clock SwitchingManish Rathi, Anand Kumar Sinha, Ateet Omer. 287-292 [doi]
• Security-aware Performance-Optimized Computation Offloading Under Near Memory ProcessingSimran Preet Kaur, Asutosh Kumar Sarma, Satanu Maity, Manojit Ghose. 293-298 [doi]
• Adaptive t-Design Dummy-Gate Obfuscation for Cryogenic-Scale EnforcementSamuel Thomas Punch, Krishnendu Guha. 299-304 [doi]
• RamForm: A Ramanujan Wavelet Transform-Based Accelerator for Energy-Efficient Signal ProcessingArya Pandit, Soham Das 0003, Arghadip Das, Debaprasad De, Arnab Raha, Mrinal Kanti Naskar. 305-310 [doi]
• m Rail to Rail OTA Achieving Uniform Small and Large Signal BehaviourMohammed Hammad Khan, Abhishek Srivastava 0002, Saurabh Zope, Ishan Acharyya. 311-316 [doi]
• An Ultra-Low-Power IoT Sensor Network for Threshold-Based Environmental MonitoringSaiotrik Ghosh, Sujatro Sarkar, Maitree Basu, Joydeep Basu. 317-322 [doi]
• Partial Product Grouping-Based Approximate Multipliers for Deep Learning InferenceBoggu Priestly Samarpana, Siddharth R. K., Geeta Shet, Nithin Kumar Y. B., Vasantha M. H.. 323-328 [doi]
• A Robust CMOS Schmitt Trigger Architecture with Improved Noise Immunity and Hysteresis ControlSiddharth R. K., Shasidhar Reddy, Cheni Deepankar, Karteek Dokala, Vasantha M. H., Nithin Kumar Y. B.. 329-334 [doi]
• Adaptive Control Strategies in DC-DC Converter for Improved Transient Response and Efficiency for High Load Slew and Fast Switching LoopsBharadwaj Subramaniam, Zia Abbas. 335-340 [doi]
• Self-Heating Aware Performance Investigation of Vertically and Sideway Stacked GAA Nanowire FETs at Sub-5nm Technology NodeGuruprasad Reddy, Jagan V, Shashidhara M, Shobhit Srivastava, Abhishek Acharya. 341-346 [doi]
• A Fully Integrated High-PSRR LDO with Cascaded NMOS-PMOS Buffer Architecture in 180 nm CMOSKaire Anupama, Patri Sreehari Rao. 347-352 [doi]
• Energy and Performance Optimized Computation Offloading for Near-Memory ComputingApratim Goswami, Satanu Maity, Manojit Ghose. 353-358 [doi]
• Scaling Limits and Reliability Challenges of Nanoscale GaN HEMTs: A Path Toward Advanced Node Benchmarking for DC and RF ApplicationsShivansh Awasthi, Vikas Kumar, Ankur Gupta. 359-364 [doi]
• IncepLite: An FPGA Based InceptionNet Accelerator for ECG Classification at Edge DevicesAnju Yajjala, Muralidhar Pullakandam, Gopala Krishna Thota. 365-370 [doi]
• Exploring Bit-Flip Attacks on DQNs with a Hash-Driven Defense AcceleratorOm Chandra Sharma, Anmol Yadav, Vihan Sachin Karnik, Palash Das 0001. 371-376 [doi]
• Cost and Communication-Aware Fast Placement of Processing Elements in Chiplets for 2.5D SystemsAyman Un Nisa, Ashok Jagannathan, Sumit K. Mandal. 377-382 [doi]
• PowerShift: Leveraging Power-Aware Weight Approximations for Neural Network AccelerationVishesh Mishra, Sparsh Mittal, Urbi Chatterjee. 383-388 [doi]
• Machine Learning Power Side-Channel Attack on SNOW-VDeepak, Rahul Balout, Anupam Golder, Suparna Kundu, Angshuman Karmakar, Debayan Das. 389-394 [doi]
• An Instruction-Set-Based Processor Design for Scalable Post-Quantum Cryptography: A Case Study with Baby KyberRamyavani P, Radhanath Mishra, Abhiram Karanam, Amit Kumar Panda, G. Geetha Kumari, Joseph Zambreno, Subhendu Kumar Sahoo. 395-400 [doi]
• NIR-DST: Noise-Immune Radiation Hardened Dual-Modal Domino-Schmitt ArchitectureHet Patel, Lakshya Singhal, Sai Ankit Sahoo, Anmol Aggarwal, Govind Prasad. 401-406 [doi]
• Probabilistic Neural Network Models for RTL DesignsHetang Patel, E. Bhawani Eswar Reddy, Chandan Karfa, Samik Das. 407-412 [doi]
• Spike-Based Time-Domain ECG Wave Delineation for Low-Power VLSI ImplementationPriya K, Binsu J. Kailath. 413-418 [doi]
• A Low-Supply, Sub-mW 1 GHz Ring Oscillator Achieving < 5% Frequency Variation Across PVT for Reliable On-Chip ClockingVellanki Venkata Sundara Raghava Chetan Krishna, Busam Karthikeya, Santosh Yachareni, Saraswatula Sree Rama Krishna Chaithnya, Abhishek Srivastava. 419-424 [doi]
• Design and Analysis of Fused SIM(S)D Functional Units for RISC-V P-and-B Extensions InstructionsNancy Gupta, David Selvakumar, Gopal Raut, Pranose J. Edavoor. 425-430 [doi]
• Exploring the Resilience Nature of AlN Cap Layer in AlGaN/GaN HEMT Under Thermal ConditionsEllapu Bhanu Prakash, Ashok Ray, Sushanta Bordoloi. 431-436 [doi]
• Post-Quantum HAWK Signature Acceleration with RISC-V-Based Hardware-Software Co-DesignRishabh Shrivastava, Utsav Banerjee. 437-442 [doi]
• A Novel Latch Reset Technique Enabling Sub-6µw Operation in Double-Tail ComparatorAditya Dubey, Sunil Rathore, Navjeet Bagga. 443-448 [doi]
• A Pipelined Probabilistic Computing Accelerator for Sparse Max-Cut with Parallel Updating p-BitsKiran Magar, Utsav Banerjee. 449-454 [doi]
• An Intelligent Digital Microfluidic Biochip System with GUI and Deep Learning-Based AutomationSanju De, Tamal Mandal, Sudip Roy 0001. 455-460 [doi]
• Low-Power Tunable Band-Pass Filter Using Unipolar Oxide TFT Technology for Wearable ApplicationsVaishali Choudhary, Suyash Shrivastava, Pydi Ganga Bahubalindruni. 461-465 [doi]
• Hardware Trojan Detection and Interpretation Using Graph Neural NetworksJayanth Thangellamudi, Negar Etemadyrad, Liang Zhao 0002, Sai Manoj P. D. 466-471 [doi]
• UniGD: A Unified Pipelined FPGA Accelerator for Analytical and Numerical Gradient Descent in Edge AIPrachi Mukherji, Seema H. Rajput, Nandini R. Kendre. 472-477 [doi]
• A Unified BIST Framework for High-Coverage Fault Detection with Area and Power MinimizationAthira J. Shenoy, Adersh V. R, Nikhil M. 478-483 [doi]
• Flash-Based Dynamic Dot Product AccelerationKyler R. Scott, Sunil P. Khatri. 484-489 [doi]
• RTL Information Tracker and its Applications in Quantifying the Security Impact of HLS OptimizationsNilotpola Sarma, Sunny Priyadarshi, Chandan Karfa. 490-495 [doi]
• A Partially Loop-Unrolled Noise-Shaping SAR ADC Achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS TechnologyAnamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele. 496-500 [doi]
• A Low Power 8-bit 3GS/s Current Steering DAC at 1.2V Supply Achieving >49 dB SFDR in 65nm CMOSAnamika Sharma, Rajesh Zele. 501-506 [doi]
• CMOSP18 FD-SOI Technology-Based IO-Ring for Testing of High-Speed ADCsManvi Dhawan, Anurup Mitra, Sathisha Seth K. 507-511 [doi]
• ThermLeT: Transformer-Based Temperature Prediction for 2.5D Chiplet ArchitectureVarun Darshana Parekh, Anusha Devulapally, Sivani Devarapalli, Cassius Henderson, Shimeng Yu, Vijaykrishnan Narayanan. 512-517 [doi]
• Machine Dynamics-Aware CPS Scheduling and Iterative Validation for Industry 4.0Pietro Turco, Enrico Fraccaroli, Samarjit Chakraborty, Franco Fummi. 518-523 [doi]
• Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix MultiplicationPragun Jaswal, L. Hemanth Krishna, B. Srinivasu. 524-529 [doi]
• Universal Formal Verification Approach for Modular Reduction CircuitsJiteshri Dasari, Maciej J. Ciesielski. 530-535 [doi]
• Energy Efficient Spiking Neural Networks for Temporal Patterns Using EvoSNN-MOMurali Krishna Yadav, B. Naresh Kumar Reddy, Yellapragada Charan Krishna, Talluri Vineel Jessy. 536-541 [doi]
• A Capacitorless On-Chip LDO for Jitter Reduction in 7.2 Gbps HBM3E PHY Clock Network with Aging and Power Delivery AnalysisJaved S. Gaggatur. 542-547 [doi]
• Accelerated IDP and EnMod-DP Hybrid Models for Robust Evacuation Navigation in Cyber-Physical Human Environments: *Benchmarking Serial vs. Parallel Architectures on Heterogeneous GridsG. Balaji, Sadanand Venkataraman, Mahendravarman M, Santhi Natarajan, G. Ravi Prakash Iyer. 548-550 [doi]