veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

Chandan Kumar Jha 0001, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan 0002, Rainer Leupers, Farhad Merchant, Rolf Drechsler. veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap., 71(9):4169-4179, September 2024. [doi]

Abstract

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