Table of Contents

• Multi-Level FeFET-Based CAM Address DecoderThomas Makryniotis, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil. 1-6 [doi]
• Embedded and Real-Time Anomalous Command Classification in Unmanned Ground Vehicle OperationsRafaella Elia, Theocharis Theocharides. 1-6 [doi]
• qCrop: An IoT Based Framework to Enhance Crop Productivity in Smart AgricultureMahdi Shamsa, Laavanya Rachakonda, Saraju P. Mohanty, Elias Kougianos. 1-6 [doi]
• Adaptive Block-Scaled GeMMs on Vector Processors for DNN Training at the EdgeNitish Satya Murthy, Nathan Laubeuf, Debjyoti Bhattacharjee, Francky Catthoor, Marian Verhelst. 1-6 [doi]
• Design Co-Processor Based on Partially Homomorphic Encryption Execution Using Open-Source ToolMujahid Bilal, M. Kamran Bhatti, Muhammad Kahsif Minhas, Haroon Waris. 1-4 [doi]
• Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL InferenceHarideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen. 1-4 [doi]
• Enhanced Diagnosis of Failing Bits in Memory Built-in Self-TestAli Shisha, Balajiraja Ravinarayanan, Knut Mellenthin. 1-4 [doi]
• An Efficient Performance-Driven Analog IC Placement Optimizer Via Extremely Randomized Tree-Based Post-Layout Performance RegressorsRicardo Martins, Nuno Lourenço. 1-4 [doi]
• SanaSolo 2.0: Edge-Based Monitoring and Management of Soil Fertility Using IoTLaavanya Rachakonda, Samuel Stasiewicz. 1-6 [doi]
• Performance Analysis of Greedy and Auction-Based Resource Allocation Algorithms in Ubiquitous Computing EnvironmentsAkshay Nagpal, Vivekananda Jayaram, Manjunatha Sughaturu Krishnappa, Nikhil Jagdish Bangad, Darshan Mohan Bidkar, Manoj Jayantilal Kathiriya, Seema G. Aarella. 1-6 [doi]
• A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAMLucas Rhetat, Jean-Philippe Noel, Bastien Giraud, Laurent Grenouillet, Julie Laguerre, Cédric Marchand 0002, Ian O'Connor. 1-6 [doi]
• A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET TechnologyMohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn. 1-5 [doi]
• Heterogeneous Approximation of DNN HW Accelerators based on Channels VulnerabilityNatalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin. 1-4 [doi]
• AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNNAsmae El Arrassi, Mohammad Amin Yaldagard, Xingjian Tao, Taha Shahroodi, Fouwad Jamil Mir, Yashvardhan Biyani, Manil Dev Gomony, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui. 1-6 [doi]
• Benchmarking Microfluidic Design Automation FlowsAshton Snelgrove, Skylar Stockham, Pierre-Emmanuel Gaillardon. 1-6 [doi]
• Compensating the Load Effect in Quadrature All-Pass FiltersUxua Esteban-Eraso, Carlos Sánchez-Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma. 1-4 [doi]
• Adaptable FWHW Formal Co-Verification of SoC RISC-V ComponentsPaulette Iskandar, Bryan Olmos, Wolfgang Kunz, Djones Lettnin. 1-6 [doi]
• A Novel Current Comparator Enabling Large RRAM Crossbars for BNNs and PUFsGokulnath Rajendran, Debajit Basak, Suman Deb, Siyi Wang, Anupam Chattopadhyay. 1-6 [doi]
• GemIMC: A Configurable HW Architecture for Technology Agnostic IMC Based NN InferenceEmilien Taly, Roberto Guizzetti, Pascal Urard, Elena Ioana Vatajelu. 1-6 [doi]
• Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA ImplementationAssia El-Hadbi, Oussama Elissati, Laurent Fesquet. 1-4 [doi]
• Diagnostic Coverage Estimation for Automotive SoCs Based on Colored Stochastic Petri NetsErnesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Michael Glaß. 1-6 [doi]
• Capture the Pulse: Impact of FPGA Resource Utilization on EM Fault Injection Attacks DetectionSami El Amraoui, Régis Leveugle, Paolo Maistri. 1-6 [doi]
• BlockShield: A TPM-Integrated Blockchain-Based Framework for Shielding Against DeepfakesVenkata K. V. V. Bathalapalli, Aakarshan Kumar, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka. 1-6 [doi]
• MCS-NTT: Multi-Chip System Design for NTT AccelerationMohammed Nabeel 0001, Homer Gamil, Johann Knechtel, Michail Maniatakos. 1-4 [doi]
• A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAMGian Singh, Ayushi Dube, Sarma B. K. Vrudhula. 1-6 [doi]
• Low Power Network-on-Chip Architecture Design TechniqueTejas Musale, Arun Ganti, Ankur Gogoi, Kanchan Manna. 1-6 [doi]
• Fortified-Edge 5.0: Federated Learning for Secure and Reliable PUF in Authentication SystemsSeema G. Aarella, Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos. 1-6 [doi]
• FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection MechanismMuhammad Kashif Minhas, Haroon Waris, Sajid Baloch. 1-4 [doi]
• MEAN: Mixture-of-Experts Based Neural ReceiverBram Van Bolderik, Vlado Menkovski, Sonia Heemstra, Manil Dev Gomony. 1-4 [doi]
• A Scalable Hardware Architecture for Efficient Learning of Recurrent Neural Networks at the EdgeYicheng Zhang, Manil Dev Gomony, Henk Corporaal, Federico Corradi. 1-4 [doi]
• Minimum Depth Quantum Modular Addition Through Carry-Save ArchitectureSiyi Wang, Eugene Lim, Xiufan Li, Jerrie Feng, Anupam Chattopadhyay. 1-6 [doi]
• Understanding Transistor Aging Impact on the Behavior of RRAM CellsSeyed Hossein Hashemi Shadmehri, Supriya Chakraborty, Thiago Santos Copetti, Fabian Luis Vargas 0001, Letícia Maria Bolzani Poehls. 1-6 [doi]
• Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ MultipliersJiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski. 1-6 [doi]
• DynaCache: A Checkpoint Aware Reconfigurable Cache for Intermittently Powered Computing SystemsRishabh Mahanta, Hemangee K. Kapoor. 1-6 [doi]
• Exploiting Functional Approximation on Decision-Tree Based Multiple Classifier SystemsMario Barbareschi, Salvatore Barone, Antonio Emmanuele, Nicola Mazzocca. 1-4 [doi]
• Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware DesignsBulbul Ahmed, Sujan Kumar Saha, Jingbo Zhou, Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi. 1-6 [doi]
• Holistic Framework for Evaluating the Trustworthiness of Integrated CircuitsMouadh Ayache, Enkele Rama, Saleh Mulhem, Mladen Berekovic, Matthias Korb. 1-4 [doi]
• Exploring the Role of the Portable Stimulus Standard in Enhancing Security Property VerificationJaimini Nagar, Thorsten Dworzak, Sebastian Simon, Ulrich Heinkel, Djones Lettnin. 1-4 [doi]
• Resource Management of Automotive Engine Control UnitsIstvan Andras Gergely, Sebastian Rausch, Nahla A. El-Araby, Axel Jantsch. 1-4 [doi]
• OSHDA: A Containerized CAD Tool for the Design and Analysis of Behavioral FSM Logic LockingEsrat Khan, Shahzad Muzaffar, Lamees M. Al Qassem, Ibrahim M. Elfadel. 1-6 [doi]
• Lightweight Active Fences for FPGAsAnis Fellah-Touta, Lilian Bossuet, Vincent Grosso, Carlos Andres Lara-Nino. 1-4 [doi]
• Transforming Agriculture: A Mini-Review of IoT Innovations and their ImpactLaavanya Rachakonda. 1-6 [doi]
• A New Control Law for N-Path Mixer Switches Enhancing Harmonic RejectionHasan Moussa, Estelle Lauga-Larroze, Laurent Fesquet. 1-4 [doi]
• Secure Software/Hardware Hybrid In-Field Testing for System-on-ChipSaleh Mulhem, Christian Ewert, Andrija Neskovic, Amrit Sharma Poudel. 1-6 [doi]
• APPAMM: Memory Management for IPsec Application on Heterogeneous SoCsAyushi Agarwal, Radhika Dharwadkar, Isaar Ahmad, Krishna Kumar, P. J. Joseph, Sourav Roy, Prokash Ghosh, Preeti Ranjan Panda. 1-6 [doi]
• 3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic SynthesisSara Mannaa, Cédric Marchand 0002, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Ian O'Connor. 1-4 [doi]
• Reliability Assessment of Large DNN Models: Trading Off Performance and AccuracyJunchao Chen 0001, Giuseppe Esposito, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Angeliki Kritikakou, Milos Krstic, Robert Limas Sierra, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Marcello Traiola, Alessandro Veronesi. 1-10 [doi]
• SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design VerificationMohammad Ismael, Ayman Hroub, Nasib Naser. 1-4 [doi]
• High-Density Standard Cell Library for Sequential 3D Integrated CircuitsArturo Prieto, Joachim Rodrigues. 1-4 [doi]
• A Unified Functional Safety EDA Framework for Accurate Diagnostic Coverage EstimationAbhiroop Bhowmik, Subin Babukutty, Mottaqiallah Taouil, Moritz Fieback. 1-6 [doi]
• FortBoot: Fortifying Rooted-in-Device-Specific Security Through Secure BootingSajeed Mohammad, Farimah Farahmandi. 1-4 [doi]
• Behavioral Simulation of Relative Timed Asynchronous CircuitsSumanth Kolluru, Kenneth S. Stevens. 1-6 [doi]
• NEATRouter: A New Method for 2D Global RoutingLuis Enrique Murillo Vizcardo, Ricardo Reis. 1-6 [doi]
• The Impact of Logic Synthesis and Technology Mapping on Logic Locking SecurityLilas Alrahis, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu. 1-6 [doi]
• In-Memory Mirroring: Cloning Without ReadingSimranjeet Singh, Ankit Bende, Chandan Kumar Jha 0001, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant. 1-6 [doi]