Table of Contents

• MERGERS: Multi-Access Edge Resource Governance for Real-Time SaaS SystemsAakashjit Bhattacharya, Arnab Sarkar, Ansuman Banerjee. 1-6 [doi]
• PrOFraC: Property Ordering and Frame Clause Reuse for Multi-Property VerificationSourav Das, Aritra Hazra, Pallab Dasgupta, Himanshu Jain, Sudipta Kundu. 7-12 [doi]
• Bidirectional Spiking Neuron Based Dual-Mode Signal Acquisition Front-End SystemTamal Chowdhury, Pradip Mandal. 13-18 [doi]
• Lichen: Leveraging Coupled HeterogeneityPrakhar Diwan, Nirmal Kumar Boran, Virendra Singh. 19-24 [doi]
• Physical Synthesis Optimization Prediction Using Machine LearningSourav Saha, Anmol Khatri, Lalit Arora, Raj Yadav, Rakshit Bazaz. 25-30 [doi]
• Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core MappingB. Naresh Kumar Reddy, Srinivasulu Jogi, Y. Charan Krishna. 31-36 [doi]
• True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFETSajjad Parvin, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler. 37-42 [doi]
• FARAD: Automated Formal Verification of Approximate Restoring Array DividersChandan Kumar Jha 0001, Khushboo Qayyum, Muhammad Hassan 0001, Rolf Drechsler. 43-48 [doi]
• CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-KyberAlip Majumdar, Rahul Shrestha. 49-54 [doi]
• hbcLock: Encrypted RF Communication Utilizing Body-Coupled Keys for the Internet of BodiesSoumick Majumdar, Anshul Madurwar, Anmol Shetty, Kurian Polachan. 55-60 [doi]
• FRoZN: Fault-Tolerant Routing Technique Using Reinforcement Learning for ZMesh NoCJitesh Choudhary, Imran Hussain Barbhuiya, Dharrun Singh. M, Soumya J.. 61-66 [doi]
• Optimal Respiratory Rate Estimation with mmWave Sensing Using PYNQ System-on-Chip PlatformMohammed Musayyeb Sherwani, Mohammad Abdul Azeem, Mohammed Usman, Siddique Ahmad, Mujeev Khan, R. Shamim, Mohd Wajid. 67-72 [doi]
• HapticGuide: Interactive Wearable Braille Guide for Enhancing Visual EducationDivyansh Singhal, Yash Gupta, Daksh Sharma, Chinmay Sultania, Madhav Rao. 73-78 [doi]
• Interconnect Optimization for Timing and Power [IOTAP]Sourav Saha, Sagar Rana, Keshav Patil, Nagamaheswar Harivelam Srinivas Gari. 79-84 [doi]
• A Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic EliminationAlexander Kharitonov, Sandip Kundu. 85-90 [doi]
• Optimizing Bandwidth Utilization Through Word Based Compression in Main MemoriesN. S. Aswathy, Harsh Verma, Hemangee K. Kapoor. 91-96 [doi]
• Accelerating U-Net: A Patchwise Memory Optimization Approach for Image SegmentationChaitanya Modiboyina, Syam Babu Gundumilli, Soumya Kanti Ghosh 0001, Indrajit Chakrabarti. 97-102 [doi]
• Pin Efficient Tri-Level Based Inductive Coupling Transceiver for 3D ICsSoumojit Bakshi, V. K. Surya, Nijwm Wary. 103-108 [doi]
• ABMF: Adaptive Bonsai Merkle Forests for Efficient Integrity Verification in Secure Persistent MemoriesHemangee K. Kapoor, Kartikay Bhardwaj. 109-114 [doi]
• A 0.27-THz Frequency Multiplier Chain Using Harmonic Mixing with Multiplication of × 18 in 65-nm CMOSBollam Shiva Prasad, Mahima Arrawatia. 115-120 [doi]
• NSGA-RM: NSGA-II Evolved Performance Optimized Non-Homogeneous Recursive Polynomial Multiplier ArchitecturesDaksh Sharma, D. R. Vasanthi, Sanampudi Gopala Krishna Reddy, Madhav Rao. 121-126 [doi]
• Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 CompressorL. Hemanth Krishna, Sreehari Veeramachaneni, Srinivasu Bodapati, Bhaskara Rao Jammu, Sk. Noor Mahammad. 127-132 [doi]
• TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory InterfaceHari Vijay Venkatanarayanan, Rustum Prasad Sahu, Maheswara Alamuru, Ergam Reddy Battini, Syed Mohammed Haroon, Saurav Suman, Deepika Mallela, Sanjeeb Kumar Ghosh, Billy Koo. 133-138 [doi]
• SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic ObfuscationJugal Gandhi, Nikhil Handa, Abhay Nayak, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey. 139-144 [doi]
• An SRAM-Based Multi-Operand Architecture Implementing Multi-Bit Boolean Functions Using in-Memory Periphery ComputingDhayan Dhananjaya Senanayake, Priyanshu Tyagi, Sparsh Mittal, Rekha Singhal. 145-150 [doi]
• Design of Manchester Carry Chain Hybrid Adder for MASH 1-1-1 Delta Sigma Modulator for Fractional-N Frequency SynthesizersAbhinav S, Busam Karthikeya, Ishan Acharyya, Anushka Tripathi, Abhishek Srivastava. 151-156 [doi]
• Boosting System-on-Chip Performance Through AI-Assisted Optimization Using Compositional Neural NetworksPriyatam Roy, Surinder Sood. 157-162 [doi]
• BMC Engine Sequencing with Graph Neural Network Embeddings of Hardware CircuitsSoumik Guha Roy, Adriz Chanda, Prateek Ganguli, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran. 163-168 [doi]
• A Constructive High-Speed Crypto-mining Approach with Dual SHA-256 on an FPGAVelamala Pavan Kumar, Aravindhan Alagarsamy. 169-174 [doi]
• A Wide Dynamic Range Differential Drive CMOS Rectifier for μWatts RF Energy Harvesting SystemsChaya Hegde, Arun Mohan 0001, Saroj Mondal, Roy P. Paily. 175-179 [doi]
• 2 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT DevicesDimple Vijay Kochar, Maitreyi Ashok, Anantha P. Chandrakasan. 180-185 [doi]
• N-Well Patterning of P-Type CMOS Substrate for Improving Quality Factor of on-Chip Inductors at Millimeter Wave FrequenciesSubbareddy Chavva, Immanuel Raja. 186-190 [doi]
• Serialized Control Interface ASIC for Distributed Controllers of Space-Borne RADARChiragkumar B. Patel, Ajay Kumar Singh, Himanshu N. Patel, B. Saravana Kumar. 191-196 [doi]
• DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware DesignsLutz Schammer, Gianluca Martino, Görschwin Fey. 197-202 [doi]
• An Innovative Solution to Improve Ultra Low Voltage Writability and Leakage in GPU SRAMsDeepesh Gujjar, Sanatkumar Upadhye, Sandipan Sinha, Taha Khursheed, Jigar Patel, Jaswinder Sidhu, Manish Trivedi, Sagar Abachi. 203-207 [doi]
• Hardware Implementation of Blind Decoding of Downlink Control Information for 5GY. Anu rajarajeswari, Nitin Chandrachoodan, Anji Babu Vadapalli, J. Klutto Milleth. 208-213 [doi]
• Startup Circuit for Relaxation Oscillators with Low Functional Current and Minimal AreaAnubhav Srivastava, Sadique Mohammad Iqbal, Divya Tripathi, Saurabh Goyal. 214-218 [doi]
• Effective Memory Management and Sparse Aware Cache for Row-Wise Sparse CNNsMC Balasubramaniam, Basava Naga Girish Koneru, Nitin Chandrachoodan. 219-224 [doi]
• FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAsHimanshu Rai, Aishwarya Sridhar, Wolfgang Ecker, Nanditha Rao. 225-230 [doi]
• Advancing Rehabilitation Through Low Weight Hand Assistive System: Design and Impact AnalysisKushagra Singh, Kafil Abbas Momin, Anshul V. Patil, Madhav Rao. 231-236 [doi]
• Advancing Neural Network Performance with Probabilistic Computing for ReLU FunctionAmit Singh, Amit Kumar Jangid, B. Srinivasu. 237-242 [doi]
• E-DOSA: Efficient Dataflow for Optimising SNN AccelerationHemangee K. Kapoor, Imlijungla Longchar, Binayak Behera. 243-248 [doi]
• Layer-Specific Hardware Pooling Designs for CNN AcceleratorsVinay Rayapati, Mahati Basavaraju, Madhav Rao. 249-254 [doi]
• TCAD Based Study of String Current Variability in 3D NAND Flash MemoryMrinmoy Mahapatra, Prathamesh Ganesh Kekarjawlekar, Akshay K.. 255-260 [doi]
• Early Bug Detector - A Verification Methodology for DFD-SoC RTL ParametersC. Bhagyalakshmi, Madhav Lekkala, Maneesh Pandey. 261-265 [doi]
• PAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main MemoriesSwati Upadhyay, Hemangee K. Kapoor. 266-271 [doi]
• A Tug-of-War Between Static and Dynamic Memory in Intel SGXSandeep Kumar, Abhisek Panda, Advait Nerlikar, Smruti R. Sarangi. 272-277 [doi]
• Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance ApplicationsAbhishek Yadav, Vyom Kumar Gupta, Kethireddy Harshith Reddy, Masahiro Fujita, Binod Kumar 0001. 278-283 [doi]
• Tunnel Magnetoresistance in Strained L10-FeAu Perpendicular Magnetic Tunnel JunctionRouf Rahman Sheikh, Ram Krishna Ghosh. 284-289 [doi]
• AI-Driven Anomaly Detection in Oscilloscope Images for Post-Silicon ValidationKowshic A. Akash, Tobias Wulf, Torsten Valentin, Alexander Geist, Ulf Kulau, Sohan Lal. 290-295 [doi]
• QuaLITi: Quantum Machine Learning Hardware Selection for Inferencing with Top-Tier PerformanceKoustubh Phalak, Swaroop Ghosh. 296-301 [doi]
• 8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET ProcessRavuru Vasudeva Reddy, Siva Kumar Rapina, Siddhartha Hazra, K. Sarangam. 302-307 [doi]
• PPA-Aware Power Grid Optimization Techniques for Congested High Frequency Datapath DesignsCheryl Mary Joyce, Parag Upadhyay, Sashank Nishad, Abhimanyu Kakkar. 308-313 [doi]
• DNA-CIM: DNA Sequence Analysis Using RRAM-Based Compute In-Memory AcceleratorJ. Chithambara Moorthii, Anmol Singla, Manan Suri. 314-319 [doi]
• K Band High Power Broadband AlGaN/GaN HEMT Balanced Power Amplifier for Satellite TransponderRitan Das, Basudev Majumder. 320-325 [doi]
• Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA DesignD. V. Bhargav, G. Pradyumna, Madhav Rao. 326-331 [doi]
• Accelerated Design Verification Coverage Closure Using Machine LearningShivani Jayakumar, Prasanth Viswanathan Pillai, Sumit Kumar Mandal. 332-337 [doi]
• Low Form-Factor Switchless Dual-Band Matching Network for RF Power Harvesting SystemsArun Mohan 0001, Saroj Mondal, Yash N. Rayudu, Roy P. Paily. 338-343 [doi]
• Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETsJaspreet Singh, Aakash Kumar Jain, Mamidala Jagadesh Kumar. 344-350 [doi]
• Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial NetworkKritanta Saha, Pritha Banerjee 0001, Susmita Sur-Kolay. 351-356 [doi]
• CMOSP18 FD-SOI Technology Based MCU Achieving High Performance of 1.2GHz Using High Speed, Optimized Leakage & High Density Tightly Coupled Memory (TCM)Praveen Verma, Anuj Dhillon, Ashfaque Ahmed, Yagnesh Vaderiya, Chandan Singh, Veenita Kumari, Harshit Sharma. 357-361 [doi]
• Low-Power and Superior Performance Design of Ternary Logic Cells Using CNFET and MOSFET Devices for VLSI ApplicationsSiva Chinmai Varma Bhupathiraju, Sridhara Sai Krishna, Yashwanth Komuravelly, Ramakant Yadav. 362-367 [doi]
• TIPAngle: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Intersection CamerasShreehari Jagadeesha, Edward Andert, Aviral Shrivastava. 368-373 [doi]
• Symmetry-Based Synthesis for Interpretable Boolean EvaluationAndrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli. 374-379 [doi]
• A Low-Power, Low-Noise, High-Performance Re-Convergent Clock Mesh Design for Large AI Compute ClustersHarivinay Kancharla, Sounil Biswas. 380-385 [doi]
• Analysis and Design Considerations for MASH of Noise Shaped SAR ADCsR. Arundeepakvel, Ankesh Jain. 386-391 [doi]
• A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory ArchitectureVarun Darshana Parekh, Yi Xiao 0008, Yixin Xu, Zijian Zhao, Zhouhang Jiang, Rudra Biswas, Sumitha George, Kai Ni 0004, Vijaykrishnan Narayanan. 392-397 [doi]
• Atrial Flutter Detection System by AdEx Encoded Lead-II ECGSushmi R, Priya K, Binsu J. Kailath. 398-403 [doi]
• Codesign for Broadcast Addressing Biochip Towards Tamper-Resistance and Enhanced ReliabilityRitwika Majumdar, Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal. 404-409 [doi]
• Advancing Functional Safety: Improving Failure Mode Analysis and Fault Injection Using Automation and GNN AlgorithmsAmurt Prakash, Abhijeet Singh, Pooja Madhusoodhanan, Padma Arvind, Viswanathan Pillai Prasanth, Sanjay Das, Kanad Basu. 410-415 [doi]
• Quantum Analysis of LESCASumanta Chakraborty, Debajyoti Mandal, SK Hafizul Islam. 416-420 [doi]
• 2D Thermal Contour Modeling of 14 nm SOI FinFET Using Machine Learning for Efficient Thermal Profile PredictionBanit Negi, Hariharan Muthusamy, Vivek Kumar. 421-426 [doi]
• An Efficient RISC-V Vector Coprocessor for Heart Rate Variability Detection on EdgeUday Kiran Pedada, Tarun Sharma, Deepank Grover, Sujay Deb. 427-432 [doi]
• Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular InversionSoham Adhikary, Ayan Palchaudhuri. 433-438 [doi]
• An Ensemble MLP-RF Model for the Prediction of DG-MOSFETs: Addressing Fabrication Process VariationsVaikunth Muthuraman, Khushwant Sehra, Vandana Kumari, Manoj Saxena. 439-444 [doi]
• LO-SC: Local-Only Split Computing for Accurate Deep Learning on Edge DevicesLuigi Capogrosso, Enrico Fraccaroli, Marco Cristani, Franco Fummi, Samarjit Chakraborty. 445-450 [doi]
• OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit QuantizationGaurav Shah, Abhinav Goud, Zaqi Momin, Joycee Mekie. 451-456 [doi]
• Novel Hardware Architectures for PRESENT Block Cipher and its FPGA RealizationsRuby Mishra, Manish Okade, Kamalakanta Mahapatra. 457-462 [doi]
• HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient ApplicationsMonika Pokharia, Het Trivedi, Siddharth Doshi, Ravi S. Hegde, Joycee Mekie. 463-468 [doi]
• TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer LevelNilotpola Sarma, Anuj Singh Thakur, Chandan Karfa. 469-474 [doi]
• Optimization of Sub-Threshold Standard Cells for Energy Efficient DesignsVardhan Suroshi, Karthik B. K, Vikram Kannur, Vinay Reddy, Madhura Purnaprajna. 475-480 [doi]
• RISC-V Based Secure Processor Architecture for Return Address ProtectionLalit Sharma, Neeraj Goel. 481-486 [doi]
• A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew CorrectionAakash Hasmukhray Mehta, Javed S. Gaggatur, Mohammad M. Rashid, Sampath Dakshinamurthy, Aruna Kumar Lakya Srinivasamurthy, Anil Kumar Goyal, Subbarao Manam, Harshit Gupta, Sandeep Sukumar, Vipin K. Mishra, Koushik N. S, Santosh Nekkanti, Sambaran Mitra, Pooja K. Jadhav, Miryala Chandra Shekar, Dudekula Humayun, Michael C. Rifani, Jianyong Xie, Andrew P. Collins. 487-492 [doi]
• Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGASantosh Kumar, Ayan Palchaudhuri. 493-498 [doi]
• A First-Principles-Based Comparative Study Between Pristine and Au-Modified Graphene Nanosheet Towards Acetaldehyde Sensing PerformanceIndranil Maity, Soubarno Chatterjee, Souvik Bhanja. 499-504 [doi]
• Robust Verification Methodology for Scan Chain in MemoriesRajat Kohli, Umang Deep, Vaishnavi Holla, Jwalant Kumar Mishra. 505-509 [doi]
• Reliable High-Performance Programmable Voltage Regulator with 0.55A Sink Current for Cryo-Cooler Electronics in 0.18μm HV-CMOS TechnologyNishant Kumar, Hari Shanker Gupta, Nihar Ranjan Mohapatra. 510-515 [doi]
• TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar ProductsMaeesha Binte Hashem, Benjamin Parpillon, Divake Kumar, Dinithi Jayasuriya, Amit Ranjan Trivedi. 516-521 [doi]
• Efficient Mitigation of DRAM Row Buffer Conflict Using Request Clustering in Manycore SystemsK. Chitra, Arjun Dey, Aryabartta Sahu. 522-527 [doi]
• A Fully Autonomous 1.2A Auxiliary Buck DC-DC Converter for Fast Transient Load-on-DemandShivam Agarwal, Sivasai Guddanti, Qadeer A. Khan. 528-533 [doi]
• MAGIC-Based High-Speed Adders for in-Memory Computing Using MemristorsShri Janani Senthil, B. Srinivasu. 534-539 [doi]
• Unguided Machine Learning-Based Computation Offloading for Near-Memory ProcessingSatanu Maity, Manojit Ghose, Avinash Kumar, Anol Chakraborty, Ankit Chakraborty. 540-545 [doi]
• LAMA: A Latency Minimum Resource Constraint Accelerator for CNN ModelsSutirtha Bhattacharyya, Fedrick Nongpoh, Karthik Maddala, E. Bhawani Eswar Reddy, Chandan Karfa. 546-551 [doi]
• Precision Clock Generation with Reference Clock Loss Tolerant Dynamic Tuning to Enable Crystal Less SSDPikul Sarkar, Nitin Gupta, Pallat Aravind, Bhavin Odedara, Dror Shahar. 552-557 [doi]
• Investigating Impact of Bit-flip Errors in Control Electronics on Quantum ComputationSubrata Das, Avimita Chatterjee, Swaroop Ghosh. 558-563 [doi]
• Enhancing Digital Microfluidic Biochip Operations with Scheduling Interval MethodNirmala N, D. Gracia Nirmala Rani. 564-568 [doi]
• An Experimental Demonstration of Neuronal Somatic Behavior Using 2D SnS Memristive Switching Characteristics and its Equivalent Circuit for Spiking Neural NetworkAnshul Awasthi, Soumi Saha, Parikshit Sahatiya, Surya Shankar Dan. 569-574 [doi]
• A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM AcceleratorAya G. Amer, Maitreyi Ashok, Xin Zhang, John Cohn, Anantha P. Chandrakasan. 575-580 [doi]