Table of Contents

• Sensitivity Enhancement of TMD MOSFET-Based Biosensor by Modeling and Optimization of Back Gate ParametersMonika Kumari, Manodipan Sahoo. 13-18 [doi]
• Design of MoS2 based Inverter Circuits considering Interface Trap effectS. Sarath, Darshni Manekar, Rajendra P. Shukla, Chandan Yadav. 43-48 [doi]
• Machine Learning based Waveform Predictions using Discrete Wavelet Transform for Automated Verification of Analog and Mixed Signal Integrated CircuitsJ. Dhurga Devi, Bama Srinivasan, Selvi Ravindran, Ranjani Parthasarathi, P. V. Ramakrishna, Lakshmanan Balasubramanian. 61-66 [doi]
• A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator in 65 nm CMOSIshan Mishra, Ganpat Anant Parulekar, Shalabh Gupta. 119-124 [doi]
• A 7.1 GHz +23.7 dBm OIP3 1-dB NF Cascode LNA for next-generation Wi-Fi using a 130 nm SOI CMOS TechnologyIndrajit Das, Hari Kishore Kakara, Vasudeva Reddy, Venkata Vanukuru. 140-144 [doi]
• A 1.6 - 2.5 GHz Receiver for Software Defined Radio with High Linearity ModeGopikrishna Vijayakumar, Alok Joshi, Abhishek Kumar 0007. 145-149 [doi]
• A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitterAnshul Verma, Bishnu Prasad Das. 156-161 [doi]
• An Integrated Multipurpose Low-Power Electrochemical Readout Interface with On-Chip Input Waveform GeneratorSayan Sarkar, Abhishek Anand. 174-179 [doi]
• SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural NetworksManu Rathore, Garrett S. Rose. 204-209 [doi]
• Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN AcceleratorMd. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury. 210-215 [doi]
• COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware AcceleratorsVrajesh Patel, Neel Shah, Aravind Krishna, Tom Glint, Abdul Ronak, Joycee Mekie. 253-258 [doi]
• Certifiable and Efficient Autonomous Cyber-Physical Systems DesignShengjie Xu, Clara Hobbs, Bineet Ghosh, Parasara Sridhar Duggirala, Samarjit Chakraborty. 259-263 [doi]
• SMT-based Control Safety Property Checking in Cyber-Physical Systems under Timing UncertaintiesAnand Yeolekar, Ravindra Metta, Samarjit Chakraborty. 276-280 [doi]
• DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI ApplicationsVinod Viswanath, Kanad Chakraborty. 293-299 [doi]
• Artificial Neural Network-based Prediction and Alleviation of Congestion during PlacementPooja Beniwal, Sneh Saurabh. 300-305 [doi]
• A Pulse Oximeter and a Controller Designed for Automatic Regulation of Oxygen ConcentratorsDibya Chowdhury, Shivdeep, Devarshi Mrinal Das. 336-341 [doi]
• Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGATamonash Bhattacharyya, Prasun Ghosal, Sonam, Sujay Deb. 372-377 [doi]
• Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with LatchesTamal Mandal, Debraj Kundu, Sudip Roy 0001. 419-424 [doi]
• Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant ApplicationsMonika Pokharia, Kailash Prasad, Ravi S. Hegde, Joycee Mekie. 431-436 [doi]
• Design for Trust Utilizing Rareness ReductionAruna Jayasena, Prabhat Mishra 0001. 437-442 [doi]
• KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGASuraj Mandal, Debapriya Basu Roy. 455-460 [doi]
• Enhancing Hardware Trojan Security through Reference-Free Clustering using RepresentativesAshutosh Ghimire, Mahommed Alkurdi, Fathi Amsaad 0001. 467-473 [doi]
• Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security PrimitiveR. Sivaraman, D. Muralidaran, Rajappa Muthaiah, V. S. Shankar Sriram. 480-485 [doi]
• Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and MultipliersVishesh Mishra, Sparsh Mittal, Nirbhay Mishra, Rekha Singhal. 511-516 [doi]
• SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP SpaceKailash Prasad, Neel Shah, Jinay Dagli, Joycee Mekie. 535-540 [doi]
• Quantifying the Efficacy of Logic Locking MethodsJoseph Sweeney, Deepali Garg, Lawrence T. Pileggi. 541-546 [doi]
• SAT and SCOPE Attacks on Deceptive Multiplexer Logic LockingJugal Gandhi, Rishi Agarwal, Anish Mall, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey. 547-552 [doi]
• Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNGGokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay. 560-564 [doi]
• Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar ArrayAnkit Bende, Simranjeet Singh, Chandan Kumar Jha 0001, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana. 565-570 [doi]
• Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided LogicChandan Kumar Jha 0001, Sallar Ahmadi-Pour, Rolf Drechsler. 577-582 [doi]
• Broadband spectrum generation in Silicon nanocrystal-based dual-slot waveguideSomen Adhikary, Ritesh Das, Mousumi Basu. 628-631 [doi]
• Generation of Asymmetric Triangular Pulse by A Dispersion and Nonlinearity Engineered Silicon Core Optical FiberAtrayee Mishra, Binoy Krishna Ghosh, Dipankar Ghosh, Mousumi Basu. 632-636 [doi]
• Wear Leveling-Aware Active Battery Cell BalancingEnrico Fraccaroli, Seongik Jang, Logan Stach, Hoeseok Yang, Sangyoung Park, Samarjit Chakraborty. 643-648 [doi]
• Power Integrity Analysis for Interoperability of BoW Chiplet InterfacesIshan Mishra, Jayaprakash Balachandran, Wen-Sin Liew, Elad Alon, Srinivas Venkataraman, Shalabh Gupta. 660-665 [doi]
• Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm OptimizationB. Naresh Kumar Reddy, Y. Charan Krishna, P. Naga Satya Nitish, Sitadevi Bharatula. 666-671 [doi]
• Evolvable Hardware for Fault Mitigation in Control CircuitsS. Deepanjali, Ayesha Shaik, Noor Mahammad Sk, Beautlin S. 672-677 [doi]
• Fault-Tolerant Floating-Point Multiplier Design for Mission Critical SystemsRaghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad. 678-683 [doi]
• On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair ModulesSabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya. 684-689 [doi]
• Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain TestingHaripriya R. S, Soumitro Vyapari, Jaynarayan T. Tudu. 712-717 [doi]