Abstract is missing.
- Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network AcceleratorsJan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina. 1-6 [doi]
- Performance and Error Tolerance of Stochastic Computing-Based Digital Filter DesignRoshwin Sengupta, Ilia Polian, John P. Hayes. 7-12 [doi]
- Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related MetricsV. Turco, Annachiara Ruospo, Ernesto Sánchez 0001, Matteo Sonza Reorda. 13-18 [doi]
- SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN AcceleratorsMahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio. 19-24 [doi]
- An Autonomous Clock Frequency Supervision CircuitClemens Scharwitzl, Andreas Steininger. 25-30 [doi]
- A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical SystemsGiorgio Cora, Corrado De Sio, Daniele Rizzieri, Sarah Azimi, Luca Sterpone. 31-36 [doi]
- The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS TechnologiesMarika Grochowska, Witold A. Pleskacz. 37-40 [doi]
- A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate EnhancementJie Pan, Fanyang Li, Yidong Yuan, Tianting Zhao, Hongwei Shen, Liguo Wen, Yi Hu, Jiazhen Jin, Shuwen Wu. 41-46 [doi]
- Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong TrackMichaela Brunner, Hye-Hyun Lee, Alexander Hepp, Johanna Baehr, Georg Sigl. 47-52 [doi]
- Fault-Simulation-Based Flip-Flop Classification for Reverse EngineeringMichael Mildner, Michaela Brunner, Michael Gruber, Johanna Baehr, Georg Sigl. 53-56 [doi]
- Optimised AES with RISC-V Vector ExtensionsMahnaz Namazi Rizi, Nusa Zidaric, Lejla Batina, Nele Mentens. 57-60 [doi]
- Xoodyak Under SCA SiegeParisa Amiri-Eliasi, Silvia Mella, Léo Weissbart, Lejla Batina, Stjepan Picek. 61-66 [doi]
- PaGoRi:A Scalable Parallel Golomb-Rice DecoderMounika Vaddeboina, Endri Kaja, Alper Yilmazer, Uttal Ghosh, Wolfgang Ecker. 67-72 [doi]
- Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction SequencesJan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler. 73-78 [doi]
- ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAsTobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich. 79-85 [doi]
- A Comparison of Logic Extraction Methods in Hardware-Translated Neural NetworksJan Schmidt, Petr Fiser, Miroslav Skrbek. 86-91 [doi]
- QDI Binary Comparator Networks and their Application in Combinational LogicFlorian Huemer. 92-97 [doi]
- An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri NetsErnesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Michael Glaß. 98-103 [doi]
- TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error DetectionRaghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh. 104-109 [doi]
- On the Fault Tolerance of Self-Supervised Training in Convolutional Neural NetworksRosario Milazzo, Vincenzo De Marco, Corrado De Sio, Sophie M. Fosson, Lia Morra, Luca Sterpone. 110-115 [doi]
- On-Chip Cross-Layer Infrastructure to Leverage System Reliability for Aero-Space Applications: Embedded TutorialFabian Luis Vargas 0001. 116-117 [doi]
- Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R ConstraintsSami El Amraoui, Régis Leveugle, Paolo Maistri. 118-123 [doi]
- Evaluating the Reliability of Integer Multipliers With Respect to Permanent FaultsNikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Serag E.-D. Habib. 124-129 [doi]
- Adaptive Input Normalization for Quantized Neural NetworksJan Schmidt, Petr Fiser, Miroslav Skrbek. 130-135 [doi]
- Interface Protection Against Transient FaultsJán Mach, Lukás Kohútka, Pavel Cicák. 136-141 [doi]
- An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGASakari Lahti, Tuomas Aaltonen, Elizaveta Rastorgueva-Foi, Jukka Talvitie, Bo Tan, Timo D. Hämäläinen. 142-147 [doi]
- A ML-Based Approach for Finding the Product Definition Space of Microelectronic Power SwitchesSeyedbehnam Beladi, Linus Maurer, Jonas Stricker, Georg Pelz. 148-151 [doi]
- Constant Voltage Maximum Power Point Tracking Method for Fully Integrated Solar-Powered Energy HarvesterAdam Hudec, Róbert Ondica, Richard Ravasz, Viera Stopjaková. 152-155 [doi]