Table of Contents

• Methods and Apparatus to Support Multiple Synchronous Clocks with a Single Clock MeshShubham Shrivastava, Sainath Kartik Yeshagol, Harry Linzer. 1-4 [doi]
• A Complete Security Protocol To Safeguard IJTAG ArchitectureNiranjana J. Ithal, Natarajan Adharsh, Anurup P, K. Sudeendra Kumar. 1-6 [doi]
• Optimizing LBIST Run Time for a Safety Critical SoC: A Practical ApproachSujeet Maurya, Gedupudi Bharghav Ram. 1-5 [doi]
• High performance advanced fault model diagnosisVaibhav Mishra, Bharath Nandakumar, Sameer Chillarige. 1-7 [doi]
• A Novel TSV Repair Framework for 3-D Stacked ICsTanusree Kaibartta, Rajiv Murmu, Debesh Kumar Das. 1-6 [doi]
• Carbon Quantum Dot Fluorescent Stickers for Biochip AuthenticationNavajit Singh Baban, Mohammed Abdelhameed, Mahmoud Elbeh, Khalil Ramadi, Yong-Ak Song, Sukanta Bhattacharjee, Ramesh Karri, Krishnendu Chakrabarty. 1-6 [doi]
• LLMs for Hardware Verification: Frameworks, Techniques, and Future DirectionsKhushboo Qayyum, Sallar Ahmadi-Pour, Chandan Kumar Jha 0001, Muhammad Hassan 0002, Rolf Drechsler. 1-6 [doi]
• Post-silicon Trace Signal Selection Using Genetic AlgorithmHanxu Feng, Yuanhang Bu, Jing Zhou, Shuo Wang, Zhuoli Wang, Lei Chen 0010. 1-4 [doi]
• A Testability Improvement Method of Combinational Circuits Based on the SDC ConditionsYang Zeng, Xiaole Cui. 1-6 [doi]
• Design and Simulation of Fault Detection Technique for NAND Based Memory ArrayJamuna S, Madhura R, Kishore Kumar K, Murali S. Bharadwaja. 1-4 [doi]
• PATROL: An Evolutionary APproach to Automatic Test Pattern Generation for Hardware TROjan Detection Leveraging PSO-GA Hybrid TechniquesMostafa Hosseini, Ali Azarpeyvand, Tara Ghasempouri. 1-6 [doi]
• Optimized Detection of Marginal Defects in Standard Cells Using Unsupervised LearningKarthik Pandaram, Hussam Amrouch, Ilia Polian. 1-6 [doi]
• Fault Testing in AI-Accelerators: A ReviewBhargab B. Bhattacharya, Debesh K. Das, Subhajit Chatterjee, Hafizur Rahaman 0001. 1-6 [doi]
• Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event ReductionJiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye 0001, Xiaowei Li 0001, Huawei Li 0001. 1-6 [doi]
• Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing ApproachDev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, F. Lalchhandama, Kamalika Datta, Rolf Drechsler, Indranil Sengupta 0001. 1-6 [doi]
• Security Vulnerabilities in AI Hardware: Threats and CountermeasuresRijoy Mukherjee, Sneha Swaroopa, Rajat Subhra Chakraborty. 1-6 [doi]
• Enhancing SRAM Array Security Through Transmission Gate-Based Logic ObfuscationBhavin Bhavani, Anupam Mathur, Sreeja Rajendran, Vinay Palaparthy, Yash Agrawal. 1-4 [doi]
• Preferential Fault-Tolerant based TF32 Floating Point Adder for Mission Critical SystemsRaghavendra Kumar Sakali, Noor Mahammad Sk. 1-5 [doi]
• Improving At-Speed Test Coverage without compromising Test Time and reducing Test Cost in multi-partition SCAN DesignJayesh Popat, Ramesh Devani, Jay Gohil. 1-5 [doi]
• Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAsVenkata Sreekanth Balijabudda, Indrajit Chakrabarti, Rajat Subhra Chakraborty. 1-6 [doi]
• LLM-aided Front-End Design Framework For Early Development of Verified RTLsVyom Kumar Gupta, Abhishek Yadav, Masahiro Fujita, Binod Kumar 0001. 1-6 [doi]
• An FPGA-Based Emulation Platform for Functional Safety Verification in Automotive SoC SystemsYutao Sun, Zhijun Wang, Zean Huang, Liping Liang. 1-6 [doi]
• Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening StrategiesGiuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 1-6 [doi]
• A Formal Approach and Testing Process for Failure Modes in Intelligent AlgorithmsNishan Xie, Hongping Ren, Rui Li, Qian Dong, Lingzhong Meng. 1-6 [doi]
• Automated System for Testing and Result Analysis for Payload ControllerAnirban Paul, Jimit Gadhia, Aashish Agrawal, Anuj Srivastava, Sandip Paul, Ashutosh Mishra, Ashok Kumar, Sanjeev Mehta, Ashish Mishra. 1-6 [doi]
• SFCM-HT: Hardware Trojan Detection Based on Sequence Features with a Combination ModelZhenghao Li, Yang Zhang, Xing Hu, Jialong Song, Shaoqing Li, Bin Liang. 1-6 [doi]
• Towards Formal Verification for MAC-based In-Memory ComputingFatemeh Shirinzadeh, Kamalika Datta, Saeideh Shirinzadeh, Abhoy Kole, Rolf Drechsler. 1-6 [doi]
• Power Aware test methodology for Test Power hungry complex SoCsPervez Garg, Piyushkumar M. Chaniyara. 1-4 [doi]
• LLM vs HLS for RTL Code Generation: Friend or Foe?Sutirtha Bhattacharyya, Sutharshanan B. G, Chandan Karfa. 1-6 [doi]
• Boosting self-repair workflow with brainstorming for code generationZhaoming Jin, Zhixin Shi. 1-6 [doi]
• Trojan Horse Detection for RISC-V Cores Using Cross-AuditingWei-Po Huang, Shi-Yu Huang, Chi-Kang Chen, Siang-Cheng Huang. 1-6 [doi]
• LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan DetectionSudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia. 1-6 [doi]
• ML Based Diagnosis for Fault Location in Digital CircuitsDiptanshu Bagchi, Habibur Rahaman, Sudip Ghosh, Subhajit Chatterjee. 1-6 [doi]
• Automotive Microcontroller Characterization Hardware - Challenges and SolutionsJithesh Pothandy Karayi, Vinodh J. Rakesh, Prince V. Thachil, Timmy Eapen Peter, Vasavi Ghanta. 1-6 [doi]
• The Future is Hybrid: Next Generation Data Structures for Formal VerificationRolf Drechsler, Christina Plump, Martha Schnieber. 1-6 [doi]
• Secure AI Systems: Emerging Threats and Defense MechanismsHabibur Rahaman, Atri Chatterjee, Swarup Bhunia. 1-6 [doi]
• SAMURAI: A Framework for Safeguarding Against Malicious Usage and Resilience of AIHabibur Rahaman, Atri Chatterjee, Swarup Bhunia. 1-6 [doi]
• RTL design of 16-bit RISC Processor Using Vedic MathematicsR. Madhura, Peram Varshitha, S. Nikitha, Niveditha K. M., Mayuri Bhat K.. 1-4 [doi]
• Finite element analysis (FEA) based design optimization of ultrastable, high finesse optical cavities for portable optical atomic clock applicationsHimanshu Miriyala, Rishabh Pal, Arijit Sharma. 1-6 [doi]
• Security Concerns of Machine Learning HardwareNilotpola Sarma, E. Bhawani Eswar Reddy, Chandan Karfa. 1-6 [doi]
• MTCX: Ultra-high Throughput TRNG Based on Mesh topology of Coupled-XORYingchun Lu, Enpu Xu, Huaguo Liang, Cuiyun Jiang, Lixiang Ma, Liang Yao. 1-4 [doi]
• A Novel Differential 12T SRAM Bit-cell Structure with Improved SNM in 16nm FinFET TechnologyJay K. Gohil, Ramesh B. Devani, Jayesh Popat. 1-7 [doi]
• A Novel Multi-Scope Characterization Method for Automotive LPDDR4 ControllerVasavi Ghanta, Vinodh J. Rakesh. 1-7 [doi]
• MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep LearningSaman Aijaz Siddiqui, Uzair Ruhulamin Patel, Utsav Jana, Binod Kumar 0001. 1-6 [doi]
• Testing Method for Embedded UltraRAM in Field Programmable Gate ArraysJiaqi Guo, Wei Xiong, Jian Wang 0036, Jinmei Lai 0001. 1-6 [doi]
• Experimental Realization of Quantum Memory and EPS-QKDDevendra Mishra, Rikteem Bhowmick, Rama Theja, Kapil Jaiswal, Devesh Kumar, Nilesh Pandey, Aishik Acharya, Bappaditya Sankhari, Sachin Barthwal. 1-6 [doi]
• RTL Agent: An Agent-Based Approach for Functionally Correct HDL Generation via LLMsSriram Ranga, Rui Mao 0010, Debjyoti Bhattacharjee, Erik Cambria, Anupam Chattopadhyay. 1-6 [doi]
• Low-cost generation of RF test stimuli from baseband digital signalsKamilia Tahraoui, T. Vayssade, François Lefèvre, Laurent Latorre, Florence Azaïs. 1-6 [doi]
• Quantum Key Distribution-Based Framework for Securing Encrypted Communications in Address Resolution Protocol Packet CaptureMohamed Yaqub A, Sudikshan S, Navin Balaji E, Adarsh A, M. Gayathri, Amlan Chakrabarti. 1-6 [doi]
• Large Language Model Driven Logic Locking: A Generative Approach to Secure IC DesignJugal Gandhi, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey. 1-4 [doi]
• FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNsSamira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Tara Ghasempouri, Christian Herglotz, Masoud Daneshtalab, Maksim Jenihhin. 1-6 [doi]
• Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected TrainingMd. Sihabul Islam, Ryota Eguchi, Michiko Inoue. 1-6 [doi]
• Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural NetworksRoshwin Sengupta, Ilia Polian, John P. Hayes. 1-6 [doi]
• Effective Runtime Fault Detection for DNN AcceleratorsWei-Kai Liu, Jonti Talukdar, Benjamin Tan 0001, Krishnendu Chakrabarty. 1-6 [doi]
• Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA FabricsJayeeta Chaudhuri, Hassan Nassar, Dennis R. E. Gnad, Jörg Henkel, Mehdi B. Tahoori, Krishnendu Chakrabarty. 1-6 [doi]