Table of Contents

• A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix ExponentialPavlos Stoikos, George Floros 0002, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George Stamoulis. 1-6 [doi]
• Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal ConsiderationHong-Wen Chiou, Jia-Hao Jiang, Yu-Teng Chang, Yu-Min Lee, Chi-Wen Pan. 7-12 [doi]
• An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMsYu-Guang Chen, Po-Yeh Huang, Jin-Fu Li. 13-18 [doi]
• Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM CrossbarsArighna Deb, Kamalika Datta, Muhammad Hassan 0002, Saeideh Shirinzadeh, Rolf Drechsler. 19-25 [doi]
• An Equivalence Checking Framework for Agile Hardware DesignYanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang. 26-32 [doi]
• Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector DuplicationBowen Liu, Dajiang Liu. 33-38 [doi]
• Safety-Driven Interactive Planning for Neural Network-Based Lane ChangingXiangguo Liu, Ruochen Jiao, Bowen Zheng, Dave Liang, Qi Zhu 0002. 39-45 [doi]
• Safety-Aware Flexible Schedule Synthesis for Cyber-Physical Systems Using Weakly-Hard ConstraintsShengjie Xu, Bineet Ghosh, Clara Hobbs, P. S. Thiagarajan, Samarjit Chakraborty. 46-51 [doi]
• Mixed-Traffic Intersection Management Utilizing Connected and Autonomous Vehicles as Traffic RegulatorsPin-Chun Chen, Xiangguo Liu, Chung-Wei Lin, Chao Huang 0015, Qi Zhu 0002. 52-57 [doi]
• Fully Automated Machine Learning Model Development for Analog Placement Quality PredictionChen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen 0001. 58-63 [doi]
• Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning ModelsF. Passos, N. Lourenço, L. Mendes, R. Martins, J. Vaz, N. Horta. 64-69 [doi]
• APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN LearningAhmet Faruk Budak, David Smart, Brian Swahn, David Z. Pan. 70-75 [doi]
• ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors All the Way up ProcessorsHussam Amrouch, Florian Klemme. 76-82 [doi]
• Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICsLilas Alrahis, Johann Knechtel, Ozgur Sinanoglu. 83-90 [doi]
• Detection and Classification of Malicious Bitstreams for FPGAs in Cloud ComputingJayeeta Chaudhuri, Krishnendu Chakrabarty. 91-97 [doi]
• Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUsJincong Lu, Jinwei Zhang, Wentian Jin, Sachin Sachdeva, Sheldon X.-D. Tan. 98-103 [doi]
• DECC: Differential ECC for Read Performance Optimization on High-Density NAND Flash MemoryYunpeng Song, Yina Lv, Liang Shi. 104-109 [doi]
• Optimizing Data Layout for Racetrack Memory in Embedded SystemsPeng Hui, Edwin H.-M. Sha, Qingfeng Zhuge, Rui Xu, Han Wang. 110-115 [doi]
• Exploring Architectural Implications to Boost Performance for in-NVM B+-TreeYanpeng Hu, Qisheng Jiang, Chundong Wang 0001. 116-121 [doi]
• An Efficient near-Bank Processing Architecture for Personalized Recommendation SystemYuQing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang 0001, Zhigang Mao, Weiguang Sheng. 122-127 [doi]
• PAALM: Power Density Aware Approximate Logarithmic Multiplier DesignShuyuan Yu, Sheldon X.-D. Tan. 128-133 [doi]
• Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy EfficiencyChenyi Wen, Ying Wu, Xunzhao Yin, Cheng Zhuo. 134-139 [doi]
• RUCA: RUntime Configurable Approximate Circuits with Self-Correcting CapabilityJingxiao Ma, Sherief Reda. 140-145 [doi]
• Approximate Logic Synthesis by Genetic Algorithm with an Error Rate GuaranteeChun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. 146-151 [doi]
• Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP CircuitsAlessandro Tempia Calvino, Giovanni De Micheli. 152-158 [doi]
• Area-Driven FPGA Logic Synthesis Using Reinforcement LearningGuanglei Zhou, Jason Helge Anderson. 159-165 [doi]
• Optimization of Reversible Logic Networks with Gate SharingYung-Chih Chen, Feng-Jie Chao. 166-171 [doi]
• Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth UtilizationStephanie Soldavini, Donatella Sciuto, Christian Pilato. 172-177 [doi]
• ViraEye: An Energy-Efficient Stereo Vision Accelerator with Binary Neural Network in 55 nm CMOSYu Zhang, Gang Chen, Tao He, Qian Huang, Kai Huang. 178-179 [doi]
• A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOSRei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda. 180-181 [doi]
• A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural NetworkYao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda. 182-183 [doi]
• A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog ProjectsKamel-Eddine Harabi, Clement Türck, Marie Drouhin, A. Renaudineau, T. Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean Michel Portal. 184-185 [doi]
• A Fully Synchronous Digital LDO with Built-in Adaptive Frequency Modulation and Implicit Dead-Zone ControlShun Yamaguchi, Mahfuzul Islam, Takashi Hisakado, Osami Wada. 186-187 [doi]
• Demonstration of Order Statistics Based Flash ADC in a 65nm ProcessMahfuzul Islam, Takehiro Kitamura, Takashi Hisakado, Osami Wada. 188-189 [doi]
• A SAT Encoding for Optimal Clifford Circuit SynthesisSarah Schneider, Lukas Burgholzer, Robert Wille. 190-195 [doi]
• An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T GatesKyohei Seino, Shigeru Yamashita. 196-201 [doi]
• Compilation of Entangling Gates for High-Dimensional Quantum SystemsKevin Mato, Martin Ringbauer, Stefan Hillmich, Robert Wille. 202-208 [doi]
• WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface CodeWang Liao, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno, Yuuki Tokunaga. 209-215 [doi]
• Quantum Data Compression for Efficient Generation of Control PulsesDaniel Volya, Prabhat Mishra 0001. 216-221 [doi]
• Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing ArchitectureYueting Li, He Zhang, Xueyan Wang, Hao Cai, Yundong Zhang, Shuqin Lv, Renguang Liu, Weisheng Zhao. 222-227 [doi]
• RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and ComputationPeiyu Chen, Meng Wu, Yufei Ma 0002, Le Ye, Ru Huang. 228-233 [doi]
• Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory AccelerationShuo Huai, Di Liu 0002, Xiangzhong Luo, Hui Chen 0016, Weichen Liu, Ravi Subramaniam. 234-239 [doi]
• Discovering the in-Memory Kernels of 3D Dot-Product EnginesMuhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Rickard Ewetz. 240-245 [doi]
• RVComp: Analog Variation Compensation for RRAM-Based in-Memory ComputingJingyu He, Yucong Huang, Miguel Lastras, Terry Tao Ye, Chi-Ying Tsui, Kwang-Ting Cheng. 246-251 [doi]
• Rethink before Releasing Your Model: ML Model Extraction Attack in EDAChen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen 0001. 252-257 [doi]
• MacroRank: Ranking Macro Placement Solutions Leveraging Translation EquivariancyYifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin. 258-263 [doi]
• BufFormer: A Generative ML Framework for Scalable BufferingRongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren. 264-270 [doi]
• Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVsDaijoon Hyun, Younggwang Jung, Insu Cho, Youngsoo Shin. 271-276 [doi]
• DPRoute: Deep Learning Framework for Package RoutingYeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen. 277-282 [doi]
• High-Dimensional Yield Estimation Using Shrinkage Deep Features and Maximization of Integral Entropy ReductionShuo Yin, Guohao Dai, Wei W. Xing. 283-289 [doi]
• MIA-Aware Detailed Placement and VT Reassignment for Leakage Power OptimizationHung-Chun Lin, Shao-Yun Fang. 290-295 [doi]
• SLOGAN: SDC Probability Estimation Using Structured Graph Attention NetworkJunchi Ma, Sulei Huang, Zongtao Duan, Lei Tang 0002, Luyang Wang. 296-301 [doi]
• Microarchitecture Power Modeling via Artificial Neural Network and Transfer LearningJianwang Zhai, Yici Cai, Bei Yu 0001. 302-307 [doi]
• MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN DataflowsHui Chen 0016, Di Liu 0002, Shiqing Li, Shuo Huai, Xiangzhong Luo, Weichen Liu. 308-313 [doi]
• COLAB: Collaborative and Efficient Processing of Replicated Cache Requests in GPUBo-Wun Cheng, En-Ming Huang, Chen-Hao Chao, Wei-Fang Sun, Tsung Tai Yeh, Chun-Yi Lee. 314-319 [doi]
• Mixed-Criticality with Integer Multiple WCETs and Dropping Relations: New Scheduling ChallengesFederico Reghenzani, William Fornaciari. 320-325 [doi]
• An Exact Schedulability Analysis for Global Fixed-Priority Scheduling of the AER Task ModelThilanka Thilakasiri, Matthias Becker 0004. 326-332 [doi]
• Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack MemorySyue-Wei Lu, Shuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang 0001, Kang Wang, Tseng-Yi Chen, Wei Kuan Shih. 333-338 [doi]
• Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit SimulationLingjie Li, Zhiqiang Liu, Kan Liu, Shan Shen, Wenjian Yu. 339-345 [doi]
• Accelerated Capacitance Simulation of 3-D Structures with Considerable Amounts of General Floating MetalsJiechen Huang, Wenjian Yu, Mingye Song, Ming Yang 0033. 346-351 [doi]
• On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADCCheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen. 352-357 [doi]
• FPGANeedle: Precise Remote Fault Attacks from FPGA to CPUMathieu Gross, Jonas Krautter, Dennis Gnad, Michael Gruber, Georg Sigl, Mehdi B. Tahoori. 358-364 [doi]
• FPGA Based Countermeasures against Side Channel Attacks on Block CiphersDarshana Jayasinghe, Brian Udugama, Sri Parameswaran. 365-371 [doi]
• Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity AnalyticsRuoyang Liu, Chenhan Wei, Yixiong Yang, Wenxun Wang, Huazhong Yang, Yongpan Liu. 372-377 [doi]
• Quantization through Search: A Novel Scheme to Quantize Convolutional Neural Networks in Finite Weight SpaceQing Lu, Weiwen Jiang, Xiaowei Xu 0004, Jingtong Hu, Yiyu Shi 0001. 378-383 [doi]
• Multi-Wavelength Parallel Training and Quantization-Aware Tuning for WDM-Based Optical Convolutional Neural Networks Considering Wavelength-Relative DeviationsYing Zhu, Min Liu, Lu Xu, Lei Wang, Xi Xiao, Shaohua Yu. 384-389 [doi]
• Semantic Guided Fine-Grained Point Cloud Quantization Framework for 3D Object DetectionXiaoyu Feng, Chen Tang, Zongkai Zhang, Wenyu Sun, Yongpan Liu. 390-395 [doi]
• ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic ComputationAli BanaGozar, Seyed Hossein Hashemi Shadmehri, Sander Stuijk, Mehdi Kamal, Ali Afzali-Kusha, Henk Corporaal. 396-401 [doi]
• SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative NetworksRohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar 0001. 402-409 [doi]
• Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural NetworksPrattay Chowdhury, Jorge Castro-Godínez, Benjamin Carrion Schafer. 410-415 [doi]
• DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled CircuitsDehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi. 416-422 [doi]
• EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced FragmentationRune Krauss, Mehran Goli, Rolf Drechsler. 423-428 [doi]
• Exploiting Reversible Computing for Verification: Potential, Possible Paths, and ConsequencesLukas Burgholzer, Robert Wille. 429-435 [doi]
• Automatic Test Pattern Generation and Compaction for Deep Neural NetworksDina Moussa, Michael Hefenbrock, Christopher Münch, Mehdi B. Tahoori. 436-441 [doi]
• Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous EffectsTakuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani. 442-448 [doi]
• Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF DesignsSimranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin Patkar, Anupam Chattopadhyay, Farhad Merchant. 449-454 [doi]
• Data Sanitization on eMMCsAya Fukami, Francesco Regazzoni 0001, Zeno J. M. H. Geradts. 455-460 [doi]
• Fundamentally Understanding and Solving RowHammerOnur Mutlu, Ataberk Olgun, Abdullah Giray Yaglikçi. 461-468 [doi]
• Hardware-Software Codesign of DNN Accelerators Using Approximate Posit MultipliersTom Glint, Kailash Prasad, Jinay Dagli, Krishil Gandhi, Aryan Gupta, Vrajesh Patel, Neel Shah, Joycee Mekie. 469-474 [doi]
• Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN AcceleratorsSusmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar. 475-482 [doi]
• BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPUMohammadHossein AskariHemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David. 483-489 [doi]
• Agile Hardware and Software Co-Design for RISC-V-Based Multi-Precision Deep Learning MicroprocessorZicheng He, Ao Shen, Qiufeng Li, Quan Cheng, Hao Yu 0001. 490-495 [doi]
• Hardware Trojan Detection Using Shapley Ensemble BoostingZhixin Pan, Prabhat Mishra 0001. 496-503 [doi]
• ASSURER: A PPA-friendly Security Closure Framework for Physical DesignGuangxin Guo, Hailong You, Zhengguang Tang, Benzheng Li, Cong Li, Xiaojue Zhang. 504-509 [doi]
• Static Probability Analysis Guided RTL Hardware Trojan Test GenerationHaoyi Wang, Qiang Zhou 0001, Yici Cai. 510-515 [doi]
• Hardware Trojan Detection and High-Precision Localization in NoC-Based MPSoC Using Machine LearningHaoyu Wang, Basel Halak. 516-521 [doi]
• An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA SystemsDan Zheng, Evangeline F. Y. Young. 522-528 [doi]
• A Robust FPGA Router with Concurrent Intra-CLB ReroutingJiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin. 529-534 [doi]
• Efficient Global Optimization for Large Scaled Ordered Escape RoutingChuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen. 535-540 [doi]
• An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance ExtractionShengkun Wu, Biwei Xie, Xingquan Li. 541-546 [doi]
• Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing AnalysisYuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi. 547-552 [doi]
• Beyond von Neumann Era: Brain-Inspired Hyperdimensional Computing to the RescueHussam Amrouch, Paul R. Genssler, Mohsen Imani, Mariam Issa, Xun Jiao, Wegdan Mohammad, Gloria Sepanta, Ruixuan Wang. 553-560 [doi]
• System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet PlatformsRafael Medina, Joshua Kein, Giovanni Ansaloni, Marina Zapater, Sergi Abadal, Eduard Alarcón, David Atienza. 561-566 [doi]
• Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace PruningYuchao Liao, Tosiron Adegbija, Roman Lysecky. 567-572 [doi]
• Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware ArchitecturesBryce Orloski, Samuel Coward, Theo Drane. 573-578 [doi]
• SHarPen: SoC Security Verification by Hardware Penetration TestHasan Al Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor. 579-584 [doi]
• SecHLS: Enabling Security Awareness in High-Level SynthesisShang Shi, Nitin Pundir, Hadi M. Kamali, Mark Tehranipoor, Farimah Farahmandi. 585-590 [doi]
• A Flexible ASIC-Oriented Design for a Full NTRU AcceleratorFrancesco Antognazza, Alessandro Barenghi, Gerardo Pelosi, Ruggero Susella. 591-597 [doi]
• Robust Hyperdimensional Computing against Cyber Attacks and Hardware Errors: A SurveyDongning Ma, Sizhe Zhang, Xun Jiao. 598-605 [doi]
• In-Memory Computing Accelerators for Emerging Learning ParadigmsDayane Reis, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu. 606-611 [doi]
• Toward Fair and Efficient Hyperdimensional ComputingYi-sheng, Junhuan Yang, Weiwen Jiang, Lei Yang. 612-617 [doi]
• Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-DesignXiaoxuan Yang, Shiyu Li, Qilin Zheng, Yiran Chen 0001. 618-623 [doi]
• Hardware-Software Co-Design for On-Chip Learning in AI SystemsM. Lakshmi Varshika, Abhishek Kumar Mishra, Nagarajan Kandasamy, Anup Das 0001. 624-631 [doi]
• Towards On-Chip Learning for Low Latency Reasoning with End-to-End SynthesisVito Giovanni Castellana, Nicolas Bohm Agostini, Ankur Limaye, Vinay Amatya, Marco Minutoli, Joseph B. Manzano, Antonino Tumeo, Serena Curzel, Michele Fiorito, Fabrizio Ferrandi. 632-638 [doi]
• Knowledge Distillation in Quantum Neural Network Using Approximate SynthesisMahabubul Alam, Satwik Kundu, Swaroop Ghosh. 639-644 [doi]
• NTGAT: A Graph Attention Network Accelerator with Runtime Node TailoringWentao Hou, Kai Zhong, Shulin Zeng, Guohao Dai, Huazhong Yang, Yu Wang 0101. 645-650 [doi]
• A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural NetworksPai-Yu Tan, Cheng-Wen Wu. 651-656 [doi]
• TiC-SAT: Tightly-Coupled Systolic Accelerator for TransformersAlireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, David Atienza. 657-663 [doi]
• PMU-Leaker: Performance Monitor Unit-Based Realization of Cache Side-Channel AttacksPengfei Qiu, Qiang Gao, Dongsheng Wang 0002, Yongqiang Lyu, Chunlu Wang, Chang Liu, Rihui Sun, Gang Qu 0001. 664-669 [doi]
• EO-Shield: A Multi-Function Protection Scheme against Side Channel and Focused Ion Beam AttacksYa Gao, Qizhi Zhang, Haocheng Ma, Jiaji He, Yiqiang Zhao. 670-675 [doi]
• CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-VJohannes Geier, Lukas Auer, Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann. 676-682 [doi]
• Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case StudySajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler. 683-689 [doi]
• Graph Partitioning Approach for Fast Quantum Circuit SimulationJaekyung Im, Seokhyeong Kang. 690-695 [doi]
• A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed StimuliHsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. 696-701 [doi]
• Equivalence Checking of Parameterized Quantum Circuits: Verifying the Compilation of Variational Quantum AlgorithmsTom Peham, Lukas Burgholzer, Robert Wille. 702-708 [doi]
• Software Tools for Decoding Quantum Low-Density Parity-Check CodesLucas Berent, Lukas Burgholzer, Robert Wille. 709-714 [doi]
• Enabling Scalable AI Computational Lithography with Physics-Inspired ModelsHaoyu Yang, Haoxing Ren. 715-720 [doi]
• Data-Driven Approaches for Process Simulation and Optical Proximity CorrectionHao-Chiang Shao, Chia-Wen Lin, Shao-Yun Fang. 721-726 [doi]
• Mixed-Type Wafer Failure Pattern RecognitionHao Geng, Qi Sun, Tinghuan Chen, Qi Xu, Tsung-Yi Ho, Bei Yu. 727-732 [doi]
• Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing ApproachBosheng Liu, Hongyi Liang, Jigang Wu, Xiaoming Chen 0003, Peng Liu, Yinhe Han. 733-738 [doi]
• Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning AccelerationYunhung Gao, Hongyan Li, Kevin Zhang, Xueru Yu, Hang Lu. 739-744 [doi]
• Data-Model-Circuit Tri-Design for Ultra-Light Video Intelligence on Edge DevicesYimeng Zhang, Akshay Karkal Kamath, Qiucheng Wu, Zhiwen Fan, Wuyang Chen, Zhangyang Wang, Shiyu Chang, Sijia Liu 0001, Cong Hao. 745-750 [doi]
• Latent Weight-Based Pruning for Small Binary Neural NetworksTianen Chen, Noah Anderson, Younghyun Kim 0001. 751-756 [doi]
• AutoFlex: Unified Evaluation and Design Framework for Flexible Hybrid ElectronicsTianliang Ma, Zhihui Deng, Leilai Shao. 757-762 [doi]
• CNFET7: An Open Source Cell Library for 7-nm CNFET TechnologyChenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda. 763-768 [doi]
• A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron CircuitsRongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen. 769-774 [doi]
• FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal SemiperimeterSven Thijssen, Sumit Kumar Jha 0001, Rickard Ewetz. 775-780 [doi]