M. ter Beek - researchr alias

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Viewing Publication 1 - 4 from 4

2005

ESD circuit model based protection network optimisation for extended-voltage NMOS driversVesselin K. Vassilev, V. A. Vashchenko, Ph. Jansen, Guido Groeseneken, M. ter Beek. mr, 45(9-11):1430-1435, 2005. [doi]

2004

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuitsVesselin K. Vassilev, Vladislav A. Vashchenko, Philippe Jansen, B. J. Choi, A. Concannon, J. J. Yang, Guido Groeseneken, M. I. Natarajan, M. ter Beek, P. Hopper, Michiel Steyaert, H. E. Maes. mr, 44(9-11):1885-1890, 2004. [doi]

2003

LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuitsV. A. Vashchenko, A. Concannon, M. ter Beek, P. Hopper. mr, 43(1):61-69, 2003. [doi]

Quasi-3D simulation approach for comparative evaluation of triggering ESD protection structuresV. A. Vashchenko, A. Concannon, M. ter Beek, P. Hopper. mr, 43(3):427-437, 2003. [doi]

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