- Yasser Ismail, Mohsen Shaaban, Jason McNeely, Magdy A. Bayoumi. An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation. IEEE Trans. VLSI Syst., 19(7):1239-1248, 2011.
- Sourajeet Roy, Anestis Dounavis. Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations. IEEE Trans. VLSI Syst., 19(2):342-346, 2011.
- Irith Pomeranz, Sudhakar M. Reddy. Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. IEEE Trans. VLSI Syst., 19(10):1755-1764, 2011.
- Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang. Design of Sequential Elements for Low Power Clocking System. IEEE Trans. VLSI Syst., 19(5):914-918, 2011.
- Renatas Jakushokas, Eby G. Friedman. Multi-Layer Interdigitated Power Distribution Networks. IEEE Trans. VLSI Syst., 19(5):774-786, 2011.
- Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang. Power Gating Aware Task Scheduling in MPSoC. IEEE Trans. VLSI Syst., 19(10):1801-1812, 2011.
- Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. IEEE Trans. VLSI Syst., 19(3):469-482, 2011.
- Yi-Ying Tsai, Chung-Ho Chen. Energy-Efficient Trace Reuse Cache for Embedded Processors. IEEE Trans. VLSI Syst., 19(9):1681-1694, 2011.
- Alexandru Andrei, Petru Eles, Olivera Jovanovic, Marcus T. Schmitz, Jens Ogniewski, Zebo Peng. Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints. IEEE Trans. VLSI Syst., 19(1):10-23, 2011.
- Stojan Z. Denic, Bane V. Vasic, Charalambos D. Charalambous, Jifeng Chen, Janet Meiling Wang. Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations. IEEE Trans. VLSI Syst., 19(3):397-410, 2011.