| 5 | -- | 6 | Naresh R. Shanbhag, Keshab K. Parhi. Guest Editorial |
| 7 | -- | 14 | Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda. QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP |
| 15 | -- | 33 | Jeongseon Euh, Jeevan Chittamuru, Wayne Burleson. Power-Aware 3D Computer Graphics Rendering |
| 35 | -- | 47 | Yanni Chen, Keshab K. Parhi. On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes |
| 49 | -- | 62 | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. Energy Efficient VLSI Architecture for Linear Turbo Equalizer |
| 63 | -- | 77 | Michael J. Thul, Frank Gilbert, Timo Vogt, Gerd Kreiselmaier, Norbert Wehn. A Scalable System Architecture for High-Throughput Turbo-Decoders |
| 79 | -- | 92 | Bruno Bougard, M. Rullmann, Erik Brockmeyer, Liesbet Van der Perre, Francky Catthoor, Wim Dehaene. Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm |
| 93 | -- | 111 | Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak. Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders |
| 113 | -- | 131 | Ying Yi, Roger Woods, Lok-Kee Ting, C. F. N. Cowan. High Speed FPGA-Based Implementations of Delayed-LMS Filters |
| 133 | -- | 146 | Tai-Lai Tung, Kung Yao. Optimum Downlink Power Control of a DS-CDMA System via Convex Programming |
| 147 | -- | 160 | Lasse Harju, Mika Kuulusa, Jari Nurmi. Flexible Implementation of a WCDMA Rake Receiver |
| 161 | -- | 173 | Thomas Richter, Gerhard Fettweis. Interleaving on Parallel DSP Architectures |
| 175 | -- | 188 | Puneet P. Newaskar, Raúl Blázquez, Anantha P. Chandrakasan. A/D Precision Requirements for Digital Ultra-Wideband Radio Receivers |