Lower-bits cache for low power STT-RAM caches

Junwhan Ahn, Kiyoung Choi. Lower-bits cache for low power STT-RAM caches. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 480-483, IEEE, 2012. [doi]

Abstract

Abstract is missing.