Analysis of a class of decimated clock/data recovery architectures for serial links

Pervez M. Aziz, Amaresh V. Malipatil. Analysis of a class of decimated clock/data recovery architectures for serial links. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 1175-1178, IEEE, 2013. [doi]

Abstract

Abstract is missing.