29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz. 29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. pages 484-485, IEEE, 2017. [doi]

Abstract

Abstract is missing.