High throughput 32-bit AES implementation in FPGA

Chi-Jeng Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen, Chung-Cheng Hsieh. High throughput 32-bit AES implementation in FPGA. In IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008. pages 1806-1809, IEEE, 2008. [doi]

Abstract

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