Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu. Majority logic circuits optimisation by node merging. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017. pages 714-719, IEEE, 2017. [doi]
Abstract is missing.