Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing - researchr publication

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Bo Fu, Paul Ampadu. Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing. In 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006. pages 1101-1104, IEEE, 2006. [doi]

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