Layer-Aware Design Partitioning for Vertical Interconnect Minimization - researchr publication

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Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang. Layer-Aware Design Partitioning for Vertical Interconnect Minimization. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India. pages 144-149, IEEE Computer Society, 2011. [doi]

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